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A new area-power efficient 4-PAM full-clock pre-emphasis CMOS transmitter for 10-Gb/s serial links is proposed. The transmitter reduces the chip area and power consumption by minimizing the number of DACs for 4-PAM pre-emphasis and the DC power consumption of each DAC. The number of DACs is set by the number of pre-emphasis taps and is independent of the number of parallel bits. The power consumption of each DAC is lowered by modulating the DC current in accordance with the level of output currents. A new full-clock multiplexing scheme is proposed to double the data rate of the widely used half-clock scheme without increasing the clock frequency. The transmitter is implemented in TSMC 0.18μm 1.8V CMOS technology and analyzed using SpectreRFM from Cadence Design Systems with BSIM3.3V transistor models and microstrip lines for channels. Simulation results are presented.