Matrix computations (3rd ed.)
Digital systems engineering
Modeling and Mitigation of Jitter in Multi-Gbps Source-Synchronous I/O Links
ICCD '03 Proceedings of the 21st International Conference on Computer Design
A Signal Integrity Test Bed for PCB Buses
ICCD '04 Proceedings of the IEEE International Conference on Computer Design
Classification of analog synthesis tools based on their architecture selection mechanisms
Integration, the VLSI Journal
Equalized interconnects for on-chip networks: modeling and optimization framework
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
Proceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design
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We present a novel method for jointly optimizing FIR filters for pre-equalization, decision feedback equalization, and near-end crosstalk cancellation. The unified optimization problem is a linear program, and we describe sparse matrix techniques for its efficient solution. We illustrate our approach with uni- and bi-directional buses using differential signaling in both intra-board and cross-backplane scenarios.