A unified optimization framework for equalization filter synthesis
Proceedings of the 42nd annual Design Automation Conference
Clocking analysis, implementation and measurement techniques for high-speed data links: a tutorial
IEEE Transactions on Circuits and Systems Part I: Regular Papers
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Jitter significantly limits the maximum achievable data rates(MADR) over high-speed source-synchronous I/O links. In this paper,we present a simple model that comprehends transmitter and receiverjitter in a source-synchronous I/O link. We show that the channelcan have a significant impact on transmit jitter at high datarates, resulting in 1.1X-3.8X jitter amplification for typicalcases. We quantify the performance degradation of transmit/receiveequalization and multi-level modulation schemes, due to jitter inhigh-speed I/O links. We present two design techniques to mitigatethe effect of jitter on performance - transmission of a slowersource-synchronous clock, and jitter equalization. Both techniquescan improve MADR by 13% when signaling over a 20" FR4 channel.