High-speed digital design: a handbook of black magic
High-speed digital design: a handbook of black magic
Digital systems engineering
Signal Integrity - Simplified
An ultralow-power 10-Gbits/s LVDS output driver
IEEE Transactions on Circuits and Systems Part I: Regular Papers
High-speed driver with built-in self detection functions for off-chip transmission
Analog Integrated Circuits and Signal Processing
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This paper describes a 12.5Gbps voltage mode transmitter with a high speed signal conditioning capability. Using a linear equalizer that is followed by a power efficient output stage, the transmitter achieves pre-emphasis at very low power consumption. In measurements, the transmitter can reliably transmit a 12.5Gbps PRBS7 signal through a lossy 14in. FR4 stripline commonly used in backplanes. It achieves a peak to peak jitter of 24ps, a differential eye opening amplitude of 120mV, and a maximum common mode ripple of 40mV. The proposed topology consumes 33mW at-speed power which includes both the output stage and the linear equalizer. It also passes 8KV HBM ESD testing without compromising the high speed capability. The transmitter is fabricated in a 130nm BiCMOS technology with 100GHz maximum f"t and packaged in a commercial leadless leadframe package.