How to use knowledge in an analysis process
DATE '99 Proceedings of the conference on Design, automation and test in Europe
An architectural solution for the inductive noise problem due to clock-gating
ISLPED '99 Proceedings of the 1999 international symposium on Low power electronics and design
Cycle-accurate energy consumption measurement and analysis: case study of ARM7TDMI
ISLPED '00 Proceedings of the 2000 international symposium on Low power electronics and design
An efficient model for frequency-dependent on-chip inductance
GLSVLSI '01 Proceedings of the 11th Great Lakes symposium on VLSI
Cycle-accurate energy measurement and characterization with a case study of the ARM7TDMI
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
IPPS '96 Proceedings of the 10th International Parallel Processing Symposium
Efficient Self-Timed Interfaces for Crossing Clock Domains
ASYNC '03 Proceedings of the 9th International Symposium on Asynchronous Circuits and Systems
Self-Calibrating Clocks for Globally Asynchronous Locally Synchronous Systems
ICCD '00 Proceedings of the 2000 IEEE International Conference on Computer Design: VLSI in Computers & Processors
S-Parameters Characterization of Through, Blind, and Buried Via Holes
IEEE Transactions on Mobile Computing
A High-Speed Transceiver Architecture Implementable as Synthesizable IP Core
Proceedings of the conference on Design, automation and test in Europe - Volume 3
A jitter characterization system using a component-invariant vernier delay line
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Jitter Models for the Design and Test of Gbps-Speed Serial Interconnects
IEEE Design & Test
Power Supply Noise in SoCs: Metrics, Management, and Measurement
IEEE Design & Test
Variable delay of multi-gigahertz digital signals for deskew and jitter-injection test applications
Proceedings of the conference on Design, automation and test in Europe
A computer-aided design tool for the analysis of electrical-connector transmission lines
International Journal of Computer Applications in Technology
System-on-Chip Test Architectures: Nanometer Design for Testability
System-on-Chip Test Architectures: Nanometer Design for Testability
Architecture and design of a simultaneously bidirectional single-ended high speed chip-to-chip interface
Development of a concept inventory test for signal and power integrity in electronic design
FIE'09 Proceedings of the 39th IEEE international conference on Frontiers in education conference
A noise-aware design and an enhanced IBIS model for evaluating simultaneous switching noise
CSECS'09 Proceedings of the 8th WSEAS International Conference on Circuits, systems, electronics, control & signal processing
A meta-level true random number generator
International Journal of Critical Computer-Based Systems
A novel design for evaluating simultaneous switching noise within an enhanced IBIS model
WSEAS Transactions on Circuits and Systems
Asynchronous current mode serial communication
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Analysis and modeling of signal integrity problems in the serial communication devices
MMES'10 Proceedings of the 2010 international conference on Mathematical models for engineering science
Layout of decoupling capacitors in IP blocks for 90-nm CMOS
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Modeling and simulation of SiC MOSFET fast switching behavior under circuit parasitics
Proceedings of the 2010 Conference on Grand Challenges in Modeling & Simulation
Efficient simulation of power/ground networks with package and vias
PATMOS'05 Proceedings of the 15th international conference on Integrated Circuit and System Design: power and Timing Modeling, Optimization and Simulation
Microelectronic Engineering
Low power high bandwidth power-line communication network for wearable applications
Proceedings of the Fifth International Conference on Body Area Networks
A multilevel fault model for integrated parallel fault-tolerant systems
Concurrency and Computation: Practice & Experience
An accurate power delivery system (PDS) design methodology for high-speed digital systems
International Journal of Circuit Theory and Applications
A 33mW 12.5Gbps BiCMOS transmitter for high speed backplane applications
Microelectronics Journal
| Hi-index | 0.00 |