Evaluating Associativity in CPU Caches
IEEE Transactions on Computers
Cache and memory hierarchy design: a performance-directed approach
Cache and memory hierarchy design: a performance-directed approach
High-speed digital design: a handbook of black magic
High-speed digital design: a handbook of black magic
IEEE Standard for Futurebust - Logical Protocol Specification: IEEE Std 896.1-1991
IEEE Standard for Futurebust - Logical Protocol Specification: IEEE Std 896.1-1991
SPAX: A New Parallel Processing System for Commercial Application
IPPS '97 Proceedings of the 11th International Symposium on Parallel Processing
On-Chip Communication Architectures: System on Chip Interconnect
On-Chip Communication Architectures: System on Chip Interconnect
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In this paper, we explore the design issues of a shared bus with pipelined protocol, so called HiPi+Bus, which is implemented for a multiprocessor server. The characteristics and design parameters for the HiPi+Bus are described. In the viewpoint of a pipelined bus, a block transfer is no good because of involving complex and unbalanced pipeline. However, it is requested by a local cache memory of which line size tends to be increased. To get the best performance and compensate unbalanced data transfer characteristic caused by block transfer, a responder queue for the bus interface is also proposed. According to the simulation results, it is explored that the HiPi+Bus, with help of the responder queue, can provide balanced service for more than 16 processors, which is important in running commercial applications. The HiPi+Bus is implemented for the TICOM III, a successor of the TICOM II which is the main server of the national administrative information network in Korea.