High-speed digital design: a handbook of black magic
High-speed digital design: a handbook of black magic
Digital signal processing (3rd ed.): principles, algorithms, and applications
Digital signal processing (3rd ed.): principles, algorithms, and applications
Proceedings of the IEEE International Test Conference on Test and Design Validity
ASYNC '96 Proceedings of the 2nd International Symposium on Advanced Research in Asynchronous Circuits and Systems
BIST for Phase-Locked Loops in Digital Applications
ITC '99 Proceedings of the 1999 IEEE International Test Conference
Self-Refereed On-Chip Jitter Measurement Circuit Using Vernier Oscillators
ISVLSI '05 Proceedings of the IEEE Computer Society Annual Symposium on VLSI: New Frontiers in VLSI Design
Jitter Decomposition by Time Lag Correlation
ISQED '06 Proceedings of the 7th International Symposium on Quality Electronic Design
A statistical study of the effectiveness of BIST jitter measurement techniques
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
A picosecond TDC architecture for multiphase PLLs
Proceedings of the 19th ACM Great Lakes symposium on VLSI
A 2.5-GHz built-in jitter measurement system in a serial-link transceiver
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A brief introduction to time-to-digital and digital-to-time converters
IEEE Transactions on Circuits and Systems II: Express Briefs
An embedded wide-range and high-resolution CLOCK jitter measurement circuit
Proceedings of the Conference on Design, Automation and Test in Europe
Investigation of single cell delay and delay mismatch in ring oscillator based test structure
ICC'06 Proceedings of the 10th WSEAS international conference on Circuits
A BIST circuit for DLL fault detection
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
High effective-resolution built-in jitter characterization with quantization noise shaping
Proceedings of the 48th Design Automation Conference
Design specification for BER analysis methods using built-in jitter measurements
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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Jitter characterization has become significantly more important for systems running at multigigahertz data rates. Time and frequency domain characterization of jitter is thus a crucial element for system specification testing. Time domain jitter measurement on a data signal with subgate timing resolution can be achieved using two delay chains feeding into the clock and datalines of a series of D-latches known as a Vernier delay line (VDL). An important drawback to the VDL structure is that its measurement accuracy depends on the matching of the various delay elements. Although careful layout techniques can help to minimize these mismatches, it cannot eliminate them completely. As well, due to the nature of the design, a relatively large silicon area is required for silicon implementation. In this paper, a novel technique is developed which reduces the silicon area requirements by two orders of magnitude, as well enables the measurement device to be synthesized from a register transfer level (RTL) description. A custom IC was designed and fabricated in a 0.18-µm CMOS process as a first proof of concept. The design requires a silicon area of 0.12 mm2 and measured results indicate a timing resolution of 19 ps. The synthesizable nature of the design is demonstrated using an field-programmable gate-array implementation. As test time is an important consideration for a production test, an extension to the component-invariant VDL technique is provided that reduces test time at the expense of more hardware. Finally, a method for obtaining the frequency domain characteristics of the jitter using the VDL will also be given.