Current Mode Techniques for Sub-pico-Ampere Circuit Design
Analog Integrated Circuits and Signal Processing
A jitter characterization system using a component-invariant vernier delay line
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A Wide-Range, High-Resolution, Compact CMOS, Time to Digital Converter
VLSID '06 Proceedings of the 19th International Conference on VLSI Design held jointly with 5th International Conference on Embedded Systems Design
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This paper presented a time-to-digital converter (TDC) embedded PLL in 3D silicon-on-insulator (SOI) process. The difficulty of tier-to-tier interconnection modeling in 3D process is very critical. The proposed TDC effectively eliminates the phase mismatches introduced by interconnection between different tiers among multiphase clocks in the 3D process. The large process variation presented in the 3D integrated circuits requires digital compensation techniques to accurately control the timing. The TDC structure presented in this paper replaced the traditional long Vernier delay line and achieved a 2ps timing resolution. A feedback structure is implemented into the TDC to eliminate the influence of the PVT variations on the timing resolution. The multiphase PLL frequency is 3.8GHz in this paper. Simulation results show that the clock jitter was decreased from 5.98ps to 3.58ps with the proposed TDC phase calibration circuit which presents a significant decrease of phase mismatches.