Measuring Jitter and Phase Error in Microprocessor Phase-Locked Loops
IEEE Design & Test
An All-Digital DFT Scheme for Testing Catastrophic Faults in PLLs
IEEE Design & Test
BIST for Phase-Locked Loops in Digital Applications
ITC '99 Proceedings of the 1999 IEEE International Test Conference
A jitter characterization system using a component-invariant vernier delay line
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Low-Area On-Chip Circuit for Jitter Measurement in a Phase-Locked Loop
IOLTS '04 Proceedings of the International On-Line Testing Symposium, 10th IEEE
Experimental Results for High-Speed Jitter Measurement Technique
ITC '04 Proceedings of the International Test Conference on International Test Conference
A statistical study of the effectiveness of BIST jitter measurement techniques
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
Purely Digital BIST for Any PLL or DLL
ETS '07 Proceedings of the 12th IEEE European Test Symposium
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A built-in-self-test (BIST) circuit for the test of a delay-locked loop circuit (DLL) is proposed. This circuit is based on a simple XNOR logic gate and uncalibrated delay lines to sample the output of the XNOR gate, so very little area overhead is introduced. In addition, no external stimulus is required for this BIST circuit, besides the "start test" signal. Fault simulation results show high fault coverage of structural faults, combined with some coverage of parametric variations.