A Method for Measuring the Cycle-to-Cycle Period Jitter of High-Frequency Clock Signals
VTS '01 Proceedings of the 19th IEEE VLSI Test Symposium
A New Method for Jitter Decomposition Through Its Distribution Tail Fitting
ITC '99 Proceedings of the 1999 IEEE International Test Conference
BIST for Phase-Locked Loops in Digital Applications
ITC '99 Proceedings of the 1999 IEEE International Test Conference
Paradigm Shift For Jitter and Noise In Design and Test GB/s Communication Systems
ICCD '03 Proceedings of the 21st International Conference on Computer Design
Random Jitter Extraction Technique in a Multi-Gigahertz Signal
Proceedings of the conference on Design, automation and test in Europe - Volume 1
A jitter characterization system using a component-invariant vernier delay line
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A HIGH-RESOLUTION FLASH TIME-TO-DIGITAL CONVERTER AND CALIBRATION SCHEME
ITC '04 Proceedings of the International Test Conference on International Test Conference
A BIST circuit for DLL fault detection
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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This paper describes a statistical study of the effectiveness of state-of-the-art built-in-self-test (BIST) jitter measurement techniques. Many BIST solutions under-sample the signal under test, estimating the jitter in a system based upon a subset of the total number of clock edges. In this paper, we explore how under-sampling affects the accuracy of jitter measurements, and demonstrate a technique for estimating the actual jitter using a Gaussian distribution estimation. Our theoretical results were verified through a simulation study and comparison to experimental data collected from a 400 MHz phase-locked loop supplied by an industry sponsor.