Jitter Models for the Design and Test of Gbps-Speed Serial Interconnects
IEEE Design & Test
Jitter Decomposition by Time Lag Correlation
ISQED '06 Proceedings of the 7th International Symposium on Quality Electronic Design
A statistical study of the effectiveness of BIST jitter measurement techniques
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
System-on-Chip Test Architectures: Nanometer Design for Testability
System-on-Chip Test Architectures: Nanometer Design for Testability
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As the communication speed/data rate approaches 1 Gb/sand beyond,timing jitter and amplitude noise become the major limiting factorsfor system performance. Traditional methods used in simulating,analyzing, modeling, and quantifying jitter and noise in terms ofpeak-to-peak and/or RMS become no longer accurate and sufficient.As such, new methods with better accuracy and comprehension arecalled for. In this paper, we will first discuss new jitter andnoise modeling and analysis methods for both design and test basedon statistical signal theory invoking probability density function(pdf) and cumulative distribution function (cdf) and thecorresponding component distributions of deterministic and randomto quantify jitter, noise, and Bit Error Rate(BER) forcommunication systems. Secondly, we will introduce jitter and noisetransfer functions and their important roles-played in estimatingrelevant jitter, noise, and BER in the system. Thirdly, we willintroduce and illustrate how those methods can be used indesigningand testing Gb/s communication systems, such as Fibre Channel(FC), Giga Bit Ethernet (GBE),and PCI Express.