ITC '02 Proceedings of the 2002 IEEE International Test Conference
A New Method for Jitter Decomposition Through Its Distribution Tail Fitting
ITC '99 Proceedings of the 1999 IEEE International Test Conference
Paradigm Shift For Jitter and Noise In Design and Test GB/s Communication Systems
ICCD '03 Proceedings of the 21st International Conference on Computer Design
A jitter characterization system using a component-invariant vernier delay line
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A Scalable On-Chip Jitter Extraction Technique
VTS '04 Proceedings of the 22nd IEEE VLSI Test Symposium
Jitter Measurements of High-Speed Serial Links
IEEE Design & Test
An Automated, Complete, Structural Test Solution for SERDES
ITC '04 Proceedings of the International Test Conference on International Test Conference
BER Estimation for Serial Links Based on Jitter Spectrum and Clock Recovery Characteristics
ITC '04 Proceedings of the International Test Conference on International Test Conference
Jitter Models and Measurement Methods for High-Speed Serial Interconnects
ITC '04 Proceedings of the International Test Conference on International Test Conference
A Better Method than Tail-fitting Algorithm for Jitter Separation Based on Gaussian Mixture Model
Journal of Electronic Testing: Theory and Applications
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Jitter decomposition is important for accurately deriving the bit-error-rate in a system and for aiding in identifying the root causes of jitter. Limits of conventional solutions to this problem are discussed and a new approach to overcome the limitations is proposed. Our method uses time lag correlation functions to decompose different jitter components. The approach is validated by hardware measurements by applying the techniques to a phase locked loop into which jitter is injected.