Jitter Decomposition by Time Lag Correlation
ISQED '06 Proceedings of the 7th International Symposium on Quality Electronic Design
2 Gbps SerDes design based on IBM Cu-11 (130nm) standard cell technology
GLSVLSI '06 Proceedings of the 16th ACM Great Lakes symposium on VLSI
On-Chip Random Jitter Testing Using Low Tap-Count Coarse Delay Lines
Journal of Electronic Testing: Theory and Applications
Digital bit stream jitter testing using jitter expansion
Proceedings of the conference on Design, automation and test in Europe
System-on-Chip Test Architectures: Nanometer Design for Testability
System-on-Chip Test Architectures: Nanometer Design for Testability
Qualifying Serial Interface Jitter Rapidly and Cost-effectively
Journal of Electronic Testing: Theory and Applications
High effective-resolution built-in jitter characterization with quantization noise shaping
Proceedings of the 48th Design Automation Conference
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Gigahertz serialization and deserialization (SERDES) has become a dominant inter-chip and interboard data transmission technique. Signal integrity is the primary factor determining its bit error rate, typically less than 10-12, so the primary production test challenges are testing picosecond jitter and the signal eye opening. Off-chip jitter and rise/fall time measurements are limited by hardware complexity, access, bandwidth, and noise. Published on-chip measurement techniques are limited by delay line jitter. This paper presents a new jitter test technique that has been demonstrated on an FPGA to achieve less than 1 ps RMS self-jitter, and a new signal eye test that has unlimited bandwidth; neither test uses high speed circuitry. The all-digital technique uses the receiver itself to demodulate the signal jitter to a low-speed bit stream that is analyzed by a single-clock domain, synthesizable circuit. This is combined with logic BIST and 1149.6 boundary scan to completely test an IC.