The architecture of the DIVA processing-in-memory chip
ICS '02 Proceedings of the 16th international conference on Supercomputing
Random Sampling for On-Chip Characterization of Standard-Cell Propagation Delay
ISQED '03 Proceedings of the 4th International Symposium on Quality Electronic Design
SERDES Technology for Gigabit I/O Communications in Storage Area Networking
IWSOC '04 Proceedings of the System-on-Chip for Real-Time Applications, 4th IEEE International Workshop
Survey of Design and Process Failure Modes for High-Speed SerDes in Nanometer CMOS
VTS '05 Proceedings of the 23rd IEEE Symposium on VLSI Test
An Automated, Complete, Structural Test Solution for SERDES
ITC '04 Proceedings of the International Test Conference on International Test Conference
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This paper introduces a standard cell based design for a Serializer and Deserializer (SerDes) communication link. The proposed design is area, power and design time efficient as compared to conventional SerDes Designs, making it very attractive for modest budget multi-core and multi-processor ASICs with wide communication buses that are difficult to accommodate within the pin count of commonly available packaging. The design employs a "Statistical Random Sampling Technique" to observe and adjust the synchronization and serialization signals at start up rather than using a resource-heavy PLL or DLL based frequency multiplier/synthesizer and clock data recovery circuits. The serialization and deserialization logic is based on standard cell technology that makes the design highly portable. Multiple serial lines are bundled with a strobe that is used as a reference signal for deserialization. Data-to-strobe timing skew is compensated by adjusting the launch times of strobe and data symbols at the sender side. The edges of the strobe are set within the eye of data symbols to have maximum timing margin, which makes the design inherently tolerant of jitter. Power consumption of the proposed SerDes design is 30 mW per serial link targeted to IBM Cu-11(130 nm) Technology, nearly a 2.5x improvement over the conventional design with a 60% less area requirement.