Survey of Design and Process Failure Modes for High-Speed SerDes in Nanometer CMOS

Authors:
Cameron Dryden
Affiliations:
Metrologic Instruments
Venue:
VTS '05 Proceedings of the 23rd IEEE Symposium on VLSI Test
Year:
2005

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Abstract

This paper gives an overview of reported design- and process-related electrical performance failure modes for high-speed (1 GHz) serial interfaces fabricated using CMOS processes ..130 nm. Effects of various defects on observable performance at the I/O pins are summarized, along with ATE test technology implications.