Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
Statistical Timing Analysis for Intra-Die Process Variations with Spatial Correlations
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
Microarchitecture and Design Challenges for Gigascale Integration
Proceedings of the 37th annual IEEE/ACM International Symposium on Microarchitecture
Stochastic Power Grid Analysis Considering Process Variations
Proceedings of the conference on Design, Automation and Test in Europe - Volume 2
Variations-aware low-power design with voltage scaling
Proceedings of the 42nd annual Design Automation Conference
Proceedings of the 42nd annual Design Automation Conference
Survey of Design and Process Failure Modes for High-Speed SerDes in Nanometer CMOS
VTS '05 Proceedings of the 23rd IEEE Symposium on VLSI Test
Process Variation Tolerant Online Current Monitor for Robust Systems
IOLTS '05 Proceedings of the 11th IEEE International On-Line Testing Symposium
The care and feeding of your statistical static timer
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
Statistical Analysis of Capacitance Coupling Effects on Delay and Noise
ISQED '06 Proceedings of the 7th International Symposium on Quality Electronic Design
Path-RO: a novel on-chip critical path delay measurement under process variations
Proceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design
Unified P4 (power-performance-process-parasitic) fast optimization of a Nano-CMOS VCO
Proceedings of the 19th ACM Great Lakes symposium on VLSI
An on-chip all-digital PV-monitoring architecture for digital IPs
PATMOS'11 Proceedings of the 21st international conference on Integrated circuit and system design: power and timing modeling, optimization, and simulation
Product on-chip process compensation for low power and yield enhancement
PATMOS'09 Proceedings of the 19th international conference on Integrated Circuit and System Design: power and Timing Modeling, Optimization and Simulation
PATMOS'09 Proceedings of the 19th international conference on Integrated Circuit and System Design: power and Timing Modeling, Optimization and Simulation
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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As device technology progresses toward 45 nm and beyond, the fidelity of process parameter modeling becomes questionable. The authors propose the concept of process variation (PV) testing, which involves applying an innovative fault model and test methodology that uses PV sensing circuitry and frequency domain analysis. Rather than pinpointing the variation of different parameters, the architecture proposed by the authors looks at the effect of PV on a chip indirectly and collectively. The novelty of this architecture is in shifting the strategy of VLSI testing to the frequency domain by using a distributed network of frequency-sensitive sensors such as ring oscillators. This provides an intrinsic advantage by minimizing the effect of noise (signal integrity loss, crosstalk, IR drop, and so on) and by using the powerful concept of digital signal processing for test analysis. The test architecture does not interfere with the rest of the circuit, thus providing freedom to tune the accuracy of PV test by choosing the proper number and type of oscillators.