Testing On-Die Process Variation in Nanometer VLSI
IEEE Design & Test
Circuit Failure Prediction and Its Application to Transistor Aging
VTS '07 Proceedings of the 25th IEEE VLSI Test Symmposium
Proceedings of the 18th ACM Great Lakes symposium on VLSI
Great Lakes Symposium on VLSI 2008
Temperature- and Voltage-Aware Timing Analysis
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Statistical Timing Analysis: From Basic Principles to State of the Art
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
A simple statistical timing analysis flow and its application to timing margin evaluation
PATMOS'07 Proceedings of the 17th international conference on Integrated Circuit and System Design: power and timing modeling, optimization and simulation
Design-in reliability for 90-65nm CMOS nodes submitted to hot-carriers and NBTI degradation
PATMOS'07 Proceedings of the 17th international conference on Integrated Circuit and System Design: power and timing modeling, optimization and simulation
SlackProbe: a low overhead in situ on-line timing slack monitoring methodology
Proceedings of the Conference on Design, Automation and Test in Europe
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PVT information is mandatory to control specific knobs to compensate the variability effects. In this paper, we propose a new on-chip monitoring system and its associated integration flow, allowing timing failure anticipation in real-time, observing the timing slack of a pre-defined set of observable flip-flops. This system is made of specific structures located nearby the flip-flops, coupled with a detection window generator, embedded within the clock-tree. Validation and performances simulated in a 45 nm technology demonstrate a scalable, low power and low area, fine-grain system. The integration flow results exhibit the weak impact of the insertion of this monitoring system toward the large benefits of tuning the circuit at its optimum working point.