Variations-aware low-power design with voltage scaling

Authors:
Navid Azizi;Muhammad M. Khellah;Vivek De;Farid N. Najm
Affiliations:
University of Toronto, Toronto, Ontario, Canada;Intel Labs, Hillsboro, OR;Intel Labs, Hillsboro, OR;University of Toronto, Toronto, Ontario, Canada
Venue:
Proceedings of the 42nd annual Design Automation Conference
Year:
2005

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Abstract

We present a new methodology which takes into consideration the effect of Within-Die (WID) process variations on a low-voltage parallel system. We show that in the presence of process variations one should use a higher supply voltage than would otherwise be predicted to minimize the power consumption of a parallel systems. Previous analyses, which ignored WID process variations, provide a lower non-optimal supply voltage which can underestimate the energy/ operation by 8.2X. We also present a novel technique to limit the effect of temperature variations in a parallel system. As temperatures increases, the scheme reduces the power increase by 43% allowing the system to remain at it's optimal supply voltage across different temperatures.