Competitive randomized algorithms for non-uniform problems
SODA '90 Proceedings of the first annual ACM-SIAM symposium on Discrete algorithms
A survey of design techniques for system-level dynamic power management
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special section on low-power electronics and design
Effectiveness of reverse body bias for leakage control in scaled dual Vt CMOS ICs
ISLPED '01 Proceedings of the 2001 international symposium on Low power electronics and design
Layout impact of resolution enhancement techniques: impediment or opportunity?
Proceedings of the 2003 international symposium on Physical design
Parameter variations and impact on circuits and microarchitecture
Proceedings of the 40th annual Design Automation Conference
Statistical timing for parametric yield prediction of digital integrated circuits
Proceedings of the 40th annual Design Automation Conference
Event-Driven Power Management of Portable Systems
Proceedings of the 12th international symposium on System synthesis
Statistical estimation of leakage current considering inter- and intra-die process variation
Proceedings of the 2003 international symposium on Low power electronics and design
Proceedings of the 2003 international symposium on Low power electronics and design
Parametric yield estimation considering leakage variability
Proceedings of the 41st annual Design Automation Conference
Tutorial 2: Leakage Issues in IC Design: Trends, Estimation, and Avoidance
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
Power Monitors: A Framework for System-Level Power Estimation Using Heterogeneous Power Models
VLSID '05 Proceedings of the 18th International Conference on VLSI Design held jointly with 4th International Conference on Embedded Systems Design
Power Variability and Its Impact on Design
VLSID '05 Proceedings of the 18th International Conference on VLSI Design held jointly with 4th International Conference on Embedded Systems Design
Full-chip analysis of leakage power under process variations, including spatial correlations
Proceedings of the 42nd annual Design Automation Conference
Variations-aware low-power design with voltage scaling
Proceedings of the 42nd annual Design Automation Conference
Power efficiency for variation-tolerant multicore processors
Proceedings of the 2006 international symposium on Low power electronics and design
Considering process variations during system-level power analysis
Proceedings of the 2006 international symposium on Low power electronics and design
Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design
TCON'95 Proceedings of the USENIX 1995 Technical Conference Proceedings
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Recovery-based design for variation-tolerant SoCs
Proceedings of the 49th Annual Design Automation Conference
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The power characteristics of system-on-chips (SoCs) in nanoscale technologies are significantly impacted by manufacturing process variations, making it important to consider these effects during system-level power analysis and optimization. In this paper, we identify and address the problem of designing effective power management schemes in the presence of such variations. In particular, we demonstrate that conventional power management schemes, which are designed without considering the impact of variations, can result in substantial power wastage. We therefore propose two approaches to variation-aware power management, namely, design-specific and chip-specific approaches. In each of these approaches, the goal is to consider the impact of variations while deriving power management policy parameters, in order to optimize metrics that are relevant under variations. We motivate and introduce these metrics, and present both exact and heuristic approaches to optimize them. The methods are designed and implemented in the context of two power management frameworks, namely an ideal oracle-based framework and a timeout-based framework. We experimentally evaluate the proposed ideas using an ARM946 processor core model. For the oracle-based framework, variation-aware power management can result in improvements of upto 59% for µ + σ, and upto 55% for 95th percentile of the energy distribution, over conventional power management schemes that do not consider variations. For the timeout-based framework, we obtain reductions of upto 43% in µ + σ and upto 55% in the 99th percentile of the energy distribution.