Proceedings of the 38th annual Design Automation Conference
Physical design methodologies for performance predictability and manufacturability
Proceedings of the 1st conference on Computing frontiers
Toward a methodology for manufacturability-driven design rule exploration
Proceedings of the 41st annual Design Automation Conference
Phase correct routing for alternating phase shift masks
Proceedings of the 41st annual Design Automation Conference
Manufacturing-Aware Physical Design
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
Technology migration technique for designs with strong RET-driven layout restrictions
Proceedings of the 2005 international symposium on Physical design
RADAR: RET-aware detailed routing using fast lithography simulations
Proceedings of the 42nd annual Design Automation Conference
Detailed placement for improved depth of focus and CD control
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
The impact of the nanoscale on computing systems
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
Process variation aware OPC with variational lithography modeling
Proceedings of the 43rd annual Design Automation Conference
Considering process variations during system-level power analysis
Proceedings of the 2006 international symposium on Low power electronics and design
Pattern sensitive placement for manufacturability
Proceedings of the 2007 international symposium on Physical design
Synergistic physical synthesis for manufacturability and variability in 45nm designs and beyond
Proceedings of the 2008 Asia and South Pacific Design Automation Conference
Design rule optimization of regular layout for leakage reduction in nanoscale design
Proceedings of the 2008 Asia and South Pacific Design Automation Conference
Wire sizing and spacing for lithographic printability and timing optimization
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
ELIAD: efficient lithography aware detailed router with compact post-OPC printability prediction
Proceedings of the 45th annual Design Automation Conference
Predictive formulae for OPC with applications to lithography-friendly routing
Proceedings of the 45th annual Design Automation Conference
An automatic optical-simulation-based lithography hotspot fix flow for post-route optimization
Proceedings of the 2009 international symposium on Physical design
Impact of lithography-friendly circuit layout
Proceedings of the 19th ACM Great Lakes symposium on VLSI
System-on-Chip Test Architectures: Nanometer Design for Testability
System-on-Chip Test Architectures: Nanometer Design for Testability
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
A framework for early and systematic evaluation of design rules
Proceedings of the 2009 International Conference on Computer-Aided Design
Variation-tolerant dynamic power management at the system-level
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A mask double patterning technique using litho simulation by wavelet transform
Proceedings of the 20th symposium on Great lakes symposium on VLSI
Predictive formulae for OPC with applications to lithography-friendly routing
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
An automatic optical simulation-based lithography hotspot fix flow for post-route optimization
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Double patterning lithography aware gridless detailed routing with innovative conflict graph
Proceedings of the 47th Design Automation Conference
ACM SIGDA Newsletter
Leakage reduction through optimization of regular layout parameters
Microelectronics Journal
Fixed origin corner square inspection layout regularity metric
DATE '12 Proceedings of the Conference on Design, Automation and Test in Europe
DATE '12 Proceedings of the Conference on Design, Automation and Test in Europe
Exact closed-form expressions for substrate resistance and capacitance extraction in nanoscale VLSI
Microelectronics Journal
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This tutorial introduces the reader to the basic concepts of optical lithography, derives fundamental resolution limits, reviews the challenges facing future technology nodes, explains the principles of resolution enhancement techniques and their impact on chip layout, and discusses layout optimization considerations.