Impact of RET on physical layouts
Proceedings of the 2001 international symposium on Physical design
Layout impact of resolution enhancement techniques: impediment or opportunity?
Proceedings of the 2003 international symposium on Physical design
A cost-driven lithographic correction methodology based on off-the-shelf sizing tools
Proceedings of the 40th annual Design Automation Conference
157-nm lithography with high numerical aperture lens for sub-70 nm node
Microelectronic Engineering
Layout Printability Optimization Using a Silicon Simulation Methodology
ISQED '04 Proceedings of the 5th International Symposium on Quality Electronic Design
Toward a methodology for manufacturability-driven design rule exploration
Proceedings of the 41st annual Design Automation Conference
Manufacturing-Aware Physical Design
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
Total solution in 157 nm lithography for below 65 nm node semiconductor devices
Microelectronic Engineering - Proceedings of the 29th international conference on micro and nano engineering
Integration Of Design For Manufacturability (DFM) Practices In Design Flows
ISQED '05 Proceedings of the 6th International Symposium on Quality of Electronic Design
RADAR: RET-aware detailed routing using fast lithography simulations
Proceedings of the 42nd annual Design Automation Conference
Backend CAD flows for "restrictive design rules"
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
Characterizing process variation in nanometer CMOS
Proceedings of the 44th annual Design Automation Conference
Modeling and analysis of non-rectangular gate for post-lithography circuit simulation
Proceedings of the 44th annual Design Automation Conference
Design rule optimization of regular layout for leakage reduction in nanoscale design
Proceedings of the 2008 Asia and South Pacific Design Automation Conference
Dose map and placement co-optimization for timing yield enhancement and leakage power reduction
Proceedings of the 45th annual Design Automation Conference
Design-process integration for performance-based OPC framework
Proceedings of the 45th annual Design Automation Conference
Cellwise OPC Based on Reduced Standard Cell Library
ISQED '08 Proceedings of the 9th international symposium on Quality Electronic Design
Semiconductor Manufacturing Handbook
Semiconductor Manufacturing Handbook
Use of lithography simulation for the calibration of equation-based design rule checks
Proceedings of the 46th Annual Design Automation Conference
Critical failure ORC: Improving model accuracy through enhanced model generation
Microelectronic Engineering
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Regular layouts that follow restrictive design rules are essential to robust CMOS design in order to alleviate many manufacturing induced effects, such as the effect of non-rectangular gate (NRG) due to sub-wavelength lithograph. NRG dramatically increases the leakage current by more than 15X compared to that of ideal physical layout. To mitigate such a penalty, we developed a technique to optimize regular layout through restrictive design rule parameters and to benchmark post-lithography circuit performance. We propose a procedure to systematically optimize key layout parameters in regular layout to minimize the leakage energy with minimal over head to active energy, circuit speed and area. The proposed layout optimization technique is demonstrated with a 65nm technology and projected for 45nm and 32nm technology nodes. Experimental results show that more than 70% reduction in leakage can be achieved with area penalty of ~10% and 9-12% overhead on circuit speed and active energy.