Layout impact of resolution enhancement techniques: impediment or opportunity?
Proceedings of the 2003 international symposium on Physical design
Advanced routing in changing technology landscape
Proceedings of the 2003 international symposium on Physical design
Research directions for coevolution of rules and routers
Proceedings of the 2003 international symposium on Physical design
Fast optical and process proximity correction algorithms for integrated circuit manufacturing
Fast optical and process proximity correction algorithms for integrated circuit manufacturing
Optical proximity correction (OPC): friendly maze routing
Proceedings of the 41st annual Design Automation Conference
Manufacturing-Aware Physical Design
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
Physical CAD changes to incorporate design for lithography and manufacturability
Proceedings of the 2004 Asia and South Pacific Design Automation Conference
Backend CAD flows for "restrictive design rules"
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
BoxRouter: a new global router based on box expansion and progressive ILP
Proceedings of the 43rd annual Design Automation Conference
Process variation aware OPC with variational lithography modeling
Proceedings of the 43rd annual Design Automation Conference
Pattern sensitive placement for manufacturability
Proceedings of the 2007 international symposium on Physical design
Efficient process-hotspot detection using range pattern matching
Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design
Modeling litho-constrained design layout
Proceedings of the 44th annual Design Automation Conference
Modeling and analysis of non-rectangular gate for post-lithography circuit simulation
Proceedings of the 44th annual Design Automation Conference
Timing-aware cell layout de-compaction for yield optimization by critical area minimization
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Accurate detection for process-hotspots with vias and incomplete specification
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
TIP-OPC: a new topological invariant paradigm for pixel based optical proximity correction
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
Synergistic physical synthesis for manufacturability and variability in 45nm designs and beyond
Proceedings of the 2008 Asia and South Pacific Design Automation Conference
Design rule optimization of regular layout for leakage reduction in nanoscale design
Proceedings of the 2008 Asia and South Pacific Design Automation Conference
Invited paper: Variability in nanometer CMOS: Impact, analysis, and minimization
Integration, the VLSI Journal
Wire sizing and spacing for lithographic printability and timing optimization
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Parallelizing CAD: a timely research agenda for EDA
Proceedings of the 45th annual Design Automation Conference
ELIAD: efficient lithography aware detailed router with compact post-OPC printability prediction
Proceedings of the 45th annual Design Automation Conference
Predictive formulae for OPC with applications to lithography-friendly routing
Proceedings of the 45th annual Design Automation Conference
An automatic optical-simulation-based lithography hotspot fix flow for post-route optimization
Proceedings of the 2009 international symposium on Physical design
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Routing for manufacturability and reliability
IEEE Circuits and Systems Magazine
Optical lithography simulation using wavelet transfor
ICCD'09 Proceedings of the 2009 IEEE international conference on Computer design
Predictive formulae for OPC with applications to lithography-friendly routing
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
An automatic optical simulation-based lithography hotspot fix flow for post-route optimization
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Modeling and analysis of the nonrectangular gate effect for postlithography circuit simulation
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Pattern sensitive placement perturbation for manufacturability
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
High performance lithographic hotspot detection using hierarchically refined machine learning
Proceedings of the 16th Asia and South Pacific Design Automation Conference
Proceedings of the 48th Design Automation Conference
Leakage reduction through optimization of regular layout parameters
Microelectronics Journal
Lithography-aware layout compaction
Proceedings of the great lakes symposium on VLSI
Improved tangent space based distance metric for accurate lithographic hotspot classification
Proceedings of the 49th Annual Design Automation Conference
Simultaneous OPC- and CMP-aware routing based on accurate closed-form modeling
Proceedings of the 2013 ACM international symposium on International symposium on physical design
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This paper attempts to reconcile the growing interdependency between nanometer lithography and physical design. We first introduce the concept of lithography hotspots and the edge placement error (EPE) map to measure the overall printability and manufacturing effort. We then adapt fast lithography simulation models to generate EPE map. Guided by EPE map, we develop effective RET-aware detailed routing (RADAR) techniques that can handle full-chip capacity to enhance the overall printability while maintaining other design closure. RADAR is implemented in an industry strength detailed router, and tested using some 65nm designs. Our experimental results show that we can achieve up to 40% EPE reduction with reasonable CPU time.