Impact of RET on physical layouts
Proceedings of the 2001 international symposium on Physical design
Layout impact of resolution enhancement techniques: impediment or opportunity?
Proceedings of the 2003 international symposium on Physical design
Toward a methodology for manufacturability-driven design rule exploration
Proceedings of the 41st annual Design Automation Conference
Manufacturing-Aware Physical Design
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
RADAR: RET-aware detailed routing using fast lithography simulations
Proceedings of the 42nd annual Design Automation Conference
Modeling and analysis of non-rectangular gate for post-lithography circuit simulation
Proceedings of the 44th annual Design Automation Conference
Semiconductor Manufacturing Handbook
Semiconductor Manufacturing Handbook
Proceedings of the 45th annual Design Automation Conference
Modeling of layout-dependent stress effect in CMOS design
Proceedings of the 2009 International Conference on Computer-Aided Design
A framework for early and systematic evaluation of design rules
Proceedings of the 2009 International Conference on Computer-Aided Design
Total sensitivity based dfm optimization of standard library cells
Proceedings of the 19th international symposium on Physical design
Leakage reduction through optimization of regular layout parameters
Microelectronics Journal
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The effect of non-rectilinear gate (NRG) due to sub-wavelength lithograph dramatically increases the leakage current by more than 15X. To mitigate this penalty, we have developed a systematic procedure to optimize key layout parameters in regular layout with minimum area and speed overhead. As demonstrated in 65nm technology, the optimization of regular layout achieves more than 70% reduction in leakage under NRG, with area penalty of ~10% and marginal impact on circuit speed and active power.