Fundamentals of modern VLSI devices
Fundamentals of modern VLSI devices
Layout design methodolgies for sub-wavelength manufacturing
Proceedings of the 38th annual Design Automation Conference
Proceedings of the 2003 international symposium on Physical design
Layout impact of resolution enhancement techniques: impediment or opportunity?
Proceedings of the 2003 international symposium on Physical design
A cost-driven lithographic correction methodology based on off-the-shelf sizing tools
Proceedings of the 40th annual Design Automation Conference
Detailed placement for improved depth of focus and CD control
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
The impact of the nanoscale on computing systems
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
An up-stream design auto-fix flow for manufacturability enhancement
Proceedings of the 43rd annual Design Automation Conference
Timing-aware cell layout de-compaction for yield optimization by critical area minimization
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Design rule optimization of regular layout for leakage reduction in nanoscale design
Proceedings of the 2008 Asia and South Pacific Design Automation Conference
A framework for early and systematic evaluation of design rules
Proceedings of the 2009 International Conference on Computer-Aided Design
Leakage reduction through optimization of regular layout parameters
Microelectronics Journal
Role of design in multiple patterning: technology development, design enablement and process control
Proceedings of the Conference on Design, Automation and Test in Europe
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Resolution enhancement techniques (RET) such as optical proximity correction (OPC) and phase-shift mask (PSM) technology are deployed in modern processes to increase the fidelity of printed features, especially critical dimensions (CD) in polysilicon. Even given these exotic technologies, there has been momentum towards less exibility in layout, in order to ensure printability. However, there has not been a systematic study of the performance and manufacturability impact of such a move towards restrictive design rules. In this paper we present a design ow that evaluates the application of various restricted design rule (RDR) sets in deep submicron ASIC designs in terms of circuit performance and parametric yield. Using such a framework, process and design engineers can identify potential solutions to maximize manufacturability by selectively applying RDRs while maintaining chip performance. In this work we focus attention on the device layer which is the most difficult design layer to manufacture. We quantify the performance, manufacturability and mask cost impact of several common design rules. For instance, we find that small increases in the minimum allowable poly line end extension beyond active provide high levels of immunity to lithographic defocus conditions. Also, modification of the minimum field poly to diffusion spacing can provide good manufacturability, while a single pitch single orientation design rule can reduce gate 3σ uncertainty. Both of these improve in data volume as well, with little to no performance penalties. Reductions in data volume and worst-case edge placement error are on the order of 20-30% and 30-50% respectively compared to a standard baseline design rule set.