Timing-aware cell layout de-compaction for yield optimization by critical area minimization

Authors:
Tetsuya Iizuka;Makoto Ikeda;Kunihiro Asada
Affiliations:
Department of Electronic Engineering, University of Tokyo, Tokyo, Japan;VLSI Design and Education Center, University of Tokyo, Tokyo, Japan;VLSI Design and Education Center, University of Tokyo, Tokyo, Japan
Venue:
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Year:
2007

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Abstract

This paper proposes a yield optimization method for standard cells under timing constraints. Yield-aware logic synthesis and physical optimization require yield enhanced standard cells and the proposed method automatically creates yield enhanced cell layouts by decompacting the original cell layout using linear programming. We develop a novel accurate linear delay model which approximates the difference from the original delay and use this model to formulate the timing constraints into linear programming. Experimental results show that the proposed method can pick up the yield variants of a cell layout from the tradeoff curve of cell delay versus critical area and is used to create the yield enhanced cell library which is essential to realize yield-aware VLSI design flows.