IBM Journal of Research and Development - Special issue: optical lithography I
Subwavelength lithography and its potential impact on design and EDA
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
A general probabilistic framework for worst case timing analysis
Proceedings of the 39th annual Design Automation Conference
Death, taxes and failing chips
Proceedings of the 40th annual Design Automation Conference
Statistical timing for parametric yield prediction of digital integrated circuits
Proceedings of the 40th annual Design Automation Conference
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Proceedings of the 2005 international symposium on Physical design
Advanced timing analysis based on post-OPC extraction of critical dimensions
Proceedings of the 42nd annual Design Automation Conference
Self-Compensating Design for Focus Variation
Proceedings of the 42nd annual Design Automation Conference
Defocus-aware leakage estimation and control
ISLPED '05 Proceedings of the 2005 international symposium on Low power electronics and design
Performance verification of high-performance ASICs using at-speed structural test
GLSVLSI '06 Proceedings of the 16th ACM Great Lakes symposium on VLSI
Process variation aware OPC with variational lithography modeling
Proceedings of the 43rd annual Design Automation Conference
Standard cell characterization considering lithography induced variations
Proceedings of the 43rd annual Design Automation Conference
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Timing-aware cell layout de-compaction for yield optimization by critical area minimization
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Proceedings of the conference on Design, automation and test in Europe
Proceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design
Manufacturability-Aware Design of Standard Cells
IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Statistical timing analysis based on simulation of lithographic process
ICCD'09 Proceedings of the 2009 IEEE international conference on Computer design
Revisiting automated physical synthesis of high-performance clock networks
ACM Transactions on Design Automation of Electronic Systems (TODAES)
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Variability of circuit performance is becoming a very important issue for ultra-deep sub-micron technology. Gate length variation has the most direct impact on circuit performance. Since many factors contribute to the variability of gate length, recent studies have modeled the variability using Gaussian distributions. In reality, the through-pitch and through-focus variations of gate length are systematic. In this paper, we propose a timing methodology which takes these systematic variations into account and we show that it can reduce the timing uncertainty by up to 40%.