A general probabilistic framework for worst case timing analysis
Proceedings of the 39th annual Design Automation Conference
Death, taxes and failing chips
Proceedings of the 40th annual Design Automation Conference
Toward a systematic-variation aware timing methodology
Proceedings of the 41st annual Design Automation Conference
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
An up-stream design auto-fix flow for manufacturability enhancement
Proceedings of the 43rd annual Design Automation Conference
Process variation aware OPC with variational lithography modeling
Proceedings of the 43rd annual Design Automation Conference
Standard cell characterization considering lithography induced variations
Proceedings of the 43rd annual Design Automation Conference
CODES+ISSS '06 Proceedings of the 4th international conference on Hardware/software codesign and system synthesis
A unified non-rectangular device and circuit simulation model for timing and power
Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design
Invited paper: Variability in nanometer CMOS: Impact, analysis, and minimization
Integration, the VLSI Journal
Electrically driven optical proximity correction based on linear programming
Proceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design
Statistical timing analysis based on simulation of lithographic process
ICCD'09 Proceedings of the 2009 IEEE international conference on Computer design
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While performance specifications are verified before sign-off for a modern nanometer scale design, extensive application of optical proximity correction substantially alters the layout introducing systematic variations to the simulated and verified performance. As a result, actual on-silicon chip performance is quite different from sign-off expectations. This paper presents a new methodology to provide better estimates of on-silicon performance. The technique relies on the extraction of residual OPC errors from placed and routed full chip layouts to derive actual (i.e., calibrated to silicon) CD values that are then used in timing analysis and speed path characterization. This approach is applied to a state-of-the-art microprocessor and contrasted with traditional design flow practices where ideal (i.e., drawn) Lgate values are employed, leading to a subsequent lack of predictive power. We present a platform for diagnosing and improving OPC quality on gates with specific functionality such as critical gates or matching transistors. Furthermore, with more accurate timing analysis we highlight the necessity of a post-OPC verification embedded design flow, by showing substantial differences in the Si-based timing simulations in terms of significant reordering of speed path criticality and a 36.4% increase in worst-case slack. Extensions of this methodology to multi-layer extraction and timing characterization are also proposed.