Subwavelength lithography and its potential impact on design and EDA
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
A general probabilistic framework for worst case timing analysis
Proceedings of the 39th annual Design Automation Conference
Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
Death, taxes and failing chips
Proceedings of the 40th annual Design Automation Conference
Toward a systematic-variation aware timing methodology
Proceedings of the 41st annual Design Automation Conference
Proceedings of the 42nd annual Design Automation Conference
Advanced timing analysis based on post-OPC extraction of critical dimensions
Proceedings of the 42nd annual Design Automation Conference
Standard cell characterization considering lithography induced variations
Proceedings of the 43rd annual Design Automation Conference
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The length of poly-gate printed on silicon depends on exposure dose, depth of focus, photo-resist thickness and planarity of the surface. In sub-wavelength lithography, polygate length also varies with layout topology. Poly-gate length determines the effective channel length of a transistor, which determines its performance. Since the sources of error are hard to control, statistical analysis can be used to measure the impact on circuit timing characteristics. Typical lithography-aware methodologies consider only systematic variation such as across chip linewidth variation (ACLV). In this paper we propose a statistical technique for timing yield prediction, based on variational lithography modeling of physical circuit layout. By statistically varying lithographic process parameters we estimate the difference in timing yield estimation of a design. Our simulation results show that if manufacturing process parameters follow a Gaussian distribution, resulting transistors follow a skewed normal distribution, where a greater number of them will have shorter channel length. This led us to investigate whether Statistical Static Timing Analysis (SSTA) is overly pessimistic. The baseline delay model assumed for SSTA in out approach is a Gaussian delay model fitted to skew normal distribution data obtained from statistical litho simulation. Our experiments showed that even after recentering Gaussian delay model to fit the channel length data with minimum error, it is still overly pessimistic and significantly underestimates circuit performance.