BooleDozer: logic synthesis for ASICs
IBM Journal of Research and Development
Fast statistical timing analysis by probabilistic event propagation
Proceedings of the 38th annual Design Automation Conference
A general probabilistic framework for worst case timing analysis
Proceedings of the 39th annual Design Automation Conference
Simulation and the Monte Carlo Method
Simulation and the Monte Carlo Method
Statistical timing analysis using bounds and selective enumeration
Proceedings of the 8th ACM/IEEE international workshop on Timing issues in the specification and synthesis of digital systems
Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
Slope propagation in static timing analysis
Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
Computation and Refinement of Statistical Bounds on Circuit Delay
Proceedings of the 40th annual Design Automation Conference
Statistical timing for parametric yield prediction of digital integrated circuits
Proceedings of the 40th annual Design Automation Conference
Timing Yield Estimation from Static Timing Analysis
ISQED '01 Proceedings of the 2nd International Symposium on Quality Electronic Design
Toward a systematic-variation aware timing methodology
Proceedings of the 41st annual Design Automation Conference
First-order incremental block-based statistical timing analysis
Proceedings of the 41st annual Design Automation Conference
A methodology to improve timing yield in the presence of process variations
Proceedings of the 41st annual Design Automation Conference
Novel sizing algorithm for yield improvement under process variation in nanometer technology
Proceedings of the 41st annual Design Automation Conference
Statistical timing analysis based on a timing yield model
Proceedings of the 41st annual Design Automation Conference
A Probabilistic Approach to Buffer Insertion
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
Manufacturing-Aware Physical Design
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
Toward stochastic design for digital circuits: statistical static timing analysis
Proceedings of the 2004 Asia and South Pacific Design Automation Conference
Empirical models for net-length probability distribution and applications
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Statistical Timing Analysis using Levelized Covariance Propagation
Proceedings of the conference on Design, Automation and Test in Europe - Volume 2
Buffer Insertion Considering Process Variation
Proceedings of the conference on Design, Automation and Test in Europe - Volume 2
Proceedings of the 2005 international symposium on Physical design
CAD for nanometer silicon design challenges and success
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Nanoelectronic circuits and systems
An efficient algorithm for statistical minimization of total power under timing yield constraints
Proceedings of the 42nd annual Design Automation Conference
Advanced timing analysis based on post-OPC extraction of critical dimensions
Proceedings of the 42nd annual Design Automation Conference
CODES+ISSS '05 Proceedings of the 3rd IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
Variability inspired implementation selection problem
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
Efficient statistical timing analysis through error budgeting
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
Backend CAD flows for "restrictive design rules"
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
Stochastic analysis of interconnect performance in the presence of process variations
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
Statistical analysis and optimization in the presence of gate and interconnect delay variations
Proceedings of the 2006 international workshop on System-level interconnect prediction
Statistical crosstalk aggressor alignment aware interconnect delay calculation
Proceedings of the 2006 international workshop on System-level interconnect prediction
Yield driven gate sizing for coupling-noise reduction under uncertainty
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
Simultaneous floorplanning and resource binding: a probabilistic approach
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
Towards formal probabilistic power-performance design space exploration
GLSVLSI '06 Proceedings of the 16th ACM Great Lakes symposium on VLSI
Crosstalk analysis in nanometer technologies
GLSVLSI '06 Proceedings of the 16th ACM Great Lakes symposium on VLSI
Statistical technology mapping for parametric yield
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
Statistical timing analysis with two-sided constraints
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
Criticality computation in parameterized statistical timing
Proceedings of the 43rd annual Design Automation Conference
Standard cell characterization considering lithography induced variations
Proceedings of the 43rd annual Design Automation Conference
CODES+ISSS '06 Proceedings of the 4th international conference on Hardware/software codesign and system synthesis
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Parametric yield in FPGAs due to within-die delay variations: a quantitative analysis
Proceedings of the 2007 ACM/SIGDA 15th international symposium on Field programmable gate arrays
Design and CAD challenges in 45nm CMOS and beyond
Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design
Yield prediction for 3D capacitive interconnections
Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design
Synthesis of a novel timing-error detection architecture
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Variations-aware low-power design and block clustering with voltage scaling
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Soft-edge flip-flops for improved timing yield: design and optimization
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
Robust gate sizing via mean excess delay minimization
Proceedings of the 2008 international symposium on Physical design
Within-die process variations: how accurately can they be statistically modeled?
Proceedings of the 2008 Asia and South Pacific Design Automation Conference
Parametric Yield Modeling and Simulations of FPGA Circuits Considering Within-Die Delay Variations
ACM Transactions on Reconfigurable Technology and Systems (TRETS)
A "true" electrical cell model for timing, noise, and power grid verification
Proceedings of the 45th annual Design Automation Conference
Challenges in gate level modeling for delay and SI at 65nm and below
Proceedings of the 45th annual Design Automation Conference
On the futility of statistical power optimization
Proceedings of the 2009 Asia and South Pacific Design Automation Conference
A fuzzy optimization approach for variation aware power minimization during gate sizing
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Impact of lithography-friendly circuit layout
Proceedings of the 19th ACM Great Lakes symposium on VLSI
Statistical static timing analysis: A survey
Integration, the VLSI Journal
Analog Integrated Circuits and Signal Processing
System-on-Chip Test Architectures: Nanometer Design for Testability
System-on-Chip Test Architectures: Nanometer Design for Testability
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Statistical timing analysis based on simulation of lithographic process
ICCD'09 Proceedings of the 2009 IEEE international conference on Computer design
Statistical leakage estimation based on sequential addition of cell leakage currents
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
On linewidth-based yield analysis for nanometer lithography
Proceedings of the Conference on Design, Automation and Test in Europe
Using randomization to cope with circuit uncertainty
Proceedings of the Conference on Design, Automation and Test in Europe
Statistical analysis of hold time violations
Journal of Computational Electronics
Evaluating statistical power optimization
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
A low power JPEG2000 encoder with iterative and fault tolerant error concealment
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Accurate estimation of SRAM dynamic stability
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A lower bound computation method for evaluation of statistical design techniques
Proceedings of the International Conference on Computer-Aided Design
Revisiting automated physical synthesis of high-performance clock networks
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Proceedings of the 50th Annual Design Automation Conference
Efficient statistical leakage analysis using deterministic cell leakage models
Microelectronics Journal
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In the way they cope with variability, present-day methodologies are onerous, pessimistic and risky, all at the same time! Dealing with variability is an increasingly important aspect of high-performance digital integrated circuit design, and indispensable for first-time-right hardware and cutting-edge performance. This invited paper discusses the methodology, analysis, synthesis and modeling aspects of this problem. These aspects of the problem are compared and contrasted in the ASIC and custom (microprocessor) domains. This paper pays particular attention to statistical timing analysis and enumerates desirable attributes that would render such an analysis capability practical and accurate.