Yield prediction for 3D capacitive interconnections

Authors:
A. Fazzi;L. Magagni;M. De Dominicis;P. Zoffoli;R. Canegallo;P. L. Rolandi;A. Sangiovanni-Vincentelli;R. Guerrieri
Affiliations:
ARCES-University of Bologna, Bologna, Italy;ARCES-University of Bologna, Bologna, Italy;ARCES-University of Bologna, Bologna, Italy;ARCES-University of Bologna, Bologna, Italy;FTM-STMicroelectronics, Agrate Brianza, Italy;FTM-STMicroelectronics, Agrate Brianza, Italy;University of California - Berkeley, CA;ARCES-University of Bologna, Bologna, Italy
Venue:
Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design
Year:
2006

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Abstract

Capacitive interconnections are very promising structures for high-speed and low-power signaling in 3D packages. Since the performance of AC links, in terms of Band-Width and Bit-Error-Rate (BER), depends on assembly and synchronization accuracy we performed a statistical analysis of assembly procedures and communication circuits. In this paper we present a yield prediction methodology for 3D capacitive links: starting from the analysis of communication circuits and BER measurements, we analyze stacking variability in order to predict reliability and performance. The proposed parametric yield analysis is demonstrated on a test-case, with constrained inter-electrode coupling and operating frequency.