Multiple Si layer ICs: motivation, performance analysis, and design implications

Authors:
Shukri J. Souri;Kaustav Banerjee;Amit Mehrotra;Krishna C. Saraswat
Affiliations:
Department of Electrical Engineering, Stanford University, Stanford, CA;Department of Electrical Engineering, Stanford University, Stanford, CA;Department of ECE, University of Illinois, Urbana-Champaign, IL and Department of Electrical Engineering, Stanford University, Stanford, CA;Department of Electrical Engineering, Stanford University, Stanford, CA
Venue:
Proceedings of the 37th Annual Design Automation Conference
Year:
2000

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Abstract

Continuous scaling of VLSI circuits is reducing gate delays but rapidly increasing interconnect delays. Semiconductor Industry Association (SIA) roadmap predicts that, beyond the 130 nm technology node, performance improvement of advanced VLSI is likely to begin to saturate unless a paradigm shift from present IC architecture is introduced. This paper presents a comprehensive analytical treatment of ICs with multiple Si layers (3-D ICs). It is shown that significant improvement in performance (more than 145%) and reduction in wire-limited chip area can be achieved with 3-D ICs with vertical inter-layer interconnects (VILICs). This analysis is based on dividing a chip into separate blocks, each occupying a separate physical level. A scheme to optimize interconnect distribution among different interconnect tiers is presented and the effect of transferring the repeaters to upper Si layers has been quantified in this analysis. Furthermore, thermal analysis of ICs with two Si layers is presented. It is demonstrated that using a thermally responsible design and/or a high-performance heat sinking technology, die temperatures for ICs with two Si layers can be reduced well below present die temperatures. Finally, implications of 3-D architecture on several circuit designs are also discussed.