Classical floorplanning harmful?
ISPD '00 Proceedings of the 2000 international symposium on Physical design
Multiple Si layer ICs: motivation, performance analysis, and design implications
Proceedings of the 37th Annual Design Automation Conference
Interconnect characteristics of 2.5-D system integration scheme
Proceedings of the 2001 international symposium on Physical design
TCG: a transitive closure graph-based representation for non-slicing floorplans
Proceedings of the 38th annual Design Automation Conference
RSP '99 Proceedings of the Tenth IEEE International Workshop on Rapid System Prototyping
Three-Dimensional Integrated Circuits: Performance, Design Methodology, and CAD Tools
ISVLSI '03 Proceedings of the IEEE Computer Society Annual Symposium on VLSI (ISVLSI'03)
A thermal-driven floorplanning algorithm for 3D ICs
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
Floorplanning for 3-D VLSI design
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
Integrating dynamic thermal via planning with 3D floorplanning algorithm
Proceedings of the 2006 international symposium on Physical design
IBM Journal of Research and Development - POWER5 and packaging
Three-dimensional integrated circuits
IBM Journal of Research and Development - Advanced silicon technology
A stable fixed-outline floorplanning method
Proceedings of the 2007 international symposium on Physical design
Large-scale fixed-outline floorplanning design using convex optimization techniques
Proceedings of the 2008 Asia and South Pacific Design Automation Conference
DeFer: deferred decision making enabled fixed-outline floorplanner
Proceedings of the 45th annual Design Automation Conference
Fixed-outline floorplanning: enabling hierarchical design
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
VLSI module placement based on rectangle-packing by the sequence-pair
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Fast evaluation of sequence pair in block placement by longest common subsequence computation
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Fixed-Outline Floorplanning: Block-Position Enumeration and a New Method for Calculating Area Costs
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
3D floorplanning of low-power and area-efficient Network-on-Chip architecture
Microprocessors & Microsystems
Practically scalable floorplanning with voltage island generation
Proceedings of the 2012 ACM/IEEE international symposium on Low power electronics and design
Fast fixed-outline 3-D IC floorplanning with TSV co-placement
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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3-D (stacked device layers) ICs can significantly alleviate the interconnect problem coming with the decreasing feature size and is promising for heterogeneous integration. In this paper, we concentrate on the configuration number and fixed-outline constraints in the floorplanning for 3-D ICs. Extended sequence pair, named partitioned sequence pair (in short, P-SP), is used to represent 3-D IC floorplans. We prove that the number of configuration of 3-D IC floorplans represented by P-SP is less than that of planar floorplans represented by sequence pair (SP) and decreases as the device layer number increases. Moreover, we applied the technique of block position enumeration, which have been successfully used in planar fixed-outline floorplanning, to fixed-outline multi-layer floorplanning. The experimental results demonstrate the efficiency and effectiveness of the proposed method.