Corner block list: an effective and efficient topological representation of non-slicing floorplan
Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
Proceedings of the 2001 IEEE/ACM international conference on Computer-aided design
Technology, performance, and computer-aided design of three-dimensional integrated circuits
Proceedings of the 2004 international symposium on Physical design
Efficient Thermal Placement of Standard Cells in 3D ICs using a Force Directed Approach
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
Thermal via placement in 3D ICs
Proceedings of the 2005 international symposium on Physical design
A thermal-driven floorplanning algorithm for 3D ICs
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
Thermal-driven multilevel routing for 3-D ICs
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
Wire congestion and thermal aware 3D global placement
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
Optimal redistribution of white space for wire length minimization
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
Thermal via planning for 3-D ICs
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
Investigating the effects of fine-grain three-dimensional integration on microarchitecture design
ACM Journal on Emerging Technologies in Computing Systems (JETC)
The road to 3D EDA tool readiness
Proceedings of the 2009 Asia and South Pacific Design Automation Conference
Allocating power ground vias in 3D ICs for simultaneous power and thermal integrity
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Temperature-constrained fixed-outline floorplanning for die-stacking system-in-package design
Proceedings of the 20th symposium on Great lakes symposium on VLSI
Multi-layer floorplanning for stacked ICs: Configuration number and fixed-outline constraints
Integration, the VLSI Journal
Energy-efficient variable-flow liquid cooling in 3D stacked architectures
Proceedings of the Conference on Design, Automation and Test in Europe
Three-dimensional integrated circuits (3D IC) floorplan and power/ground network co-synthesis
Proceedings of the 2010 Asia and South Pacific Design Automation Conference
Fixed-outline thermal-aware 3D floorplanning
Proceedings of the 2010 Asia and South Pacific Design Automation Conference
Assembling 2D blocks into 3D chips
Proceedings of the 2011 international symposium on Physical design
Thermal via allocation for 3-D ICs considering temporally and spatially variant thermal power
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Fuzzy control for enforcing energy efficiency in high-performance 3D systems
Proceedings of the International Conference on Computer-Aided Design
Design-time performance evaluation of thermal management policies for SRAM and RRAM based 3D MPSoCs
Proceedings of the great lakes symposium on VLSI
Multiobjective optimization of deadspace, a critical resource for 3D-IC integration
Proceedings of the International Conference on Computer-Aided Design
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Incorporating thermal vias into 3D ICs is a promising way to reduce circuit temperature by lowering down the thermal resistances between device layers. In this paper, we integrate dynamic thermal via planning into 3D floorplanning process. Our 3D floorplanning and thermal via planning approaches are implemented in a two-stage approach. Before floorplanning, the temperature-constrained vertical thermal via planning is formulated as a convex programming problem. Based on the analytical solution, blocks are assigned into different layers by solving a sequence of knapsack problems. Then a SA engine is used to generate floorplans of all these layers simultaneously. During floorplanning, thermal vias are distributed horizontally in each layer with white space redistribution to optimize thermal via insertion. Experimental results show that compared to a recent published result from [14], our method can reduce thermal vias by 15% with 38% runtime overhead.