A matrix synthesis approach to thermal placement
Proceedings of the 1997 international symposium on Physical design
Generic global placement and floorplanning
DAC '98 Proceedings of the 35th annual Design Automation Conference
A First Course in the Finite Element Method Using Algor
A First Course in the Finite Element Method Using Algor
A force-directed macro-cell placer
Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
Partition-driven standard cell thermal placement
Proceedings of the 2003 international symposium on Physical design
Cell-level placement for improving substrate thermal distribution
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Thermal via placement in 3D ICs
Proceedings of the 2005 international symposium on Physical design
Implementing Caches in a 3D Technology for High Performance Processors
ICCD '05 Proceedings of the 2005 International Conference on Computer Design
Temperature-Aware Voltage Islands Architecting in System-on-Chip Design
ICCD '05 Proceedings of the 2005 International Conference on Computer Design
Placement and Routing in 3D Integrated Circuits
IEEE Design & Test
A thermal-driven floorplanning algorithm for 3D ICs
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
Efficient full-chip thermal modeling and analysis
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
Engineering details of a stable force-directed placer
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
Electrothermal analysis and optimization techniques for nanoscale integrated circuits
ASP-DAC '06 Proceedings of the 2006 Asia and South Pacific Design Automation Conference
Temperature-aware routing in 3D ICs
ASP-DAC '06 Proceedings of the 2006 Asia and South Pacific Design Automation Conference
TAPHS: thermal-aware unified physical-level and high-level synthesis
ASP-DAC '06 Proceedings of the 2006 Asia and South Pacific Design Automation Conference
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
On-chip thermal gradient analysis and temperature flattening for SoC design
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
Wire congestion and thermal aware 3D global placement
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
Three-dimensional place and route for FPGAs
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
Integrating dynamic thermal via planning with 3D floorplanning algorithm
Proceedings of the 2006 international symposium on Physical design
Interconnect and Thermal-aware Floorplanning for 3D Microprocessors
ISQED '06 Proceedings of the 7th International Symposium on Quality Electronic Design
Thermal analysis of a 3D die-stacked high-performance microprocessor
GLSVLSI '06 Proceedings of the 16th ACM Great Lakes symposium on VLSI
Dynamic instruction schedulers in a 3-dimensional integration technology
GLSVLSI '06 Proceedings of the 16th ACM Great Lakes symposium on VLSI
A high efficiency full-chip thermal simulation algorithm
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
Thermal via planning for 3-D ICs
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
Efficient thermal-oriented 3D floorplanning and thermal via planning for two-stacked-die integration
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Exploring compromises among timing, power and temperature in three-dimensional integrated circuits
Proceedings of the 43rd annual Design Automation Conference
Design space exploration for 3D architectures
ACM Journal on Emerging Technologies in Computing Systems (JETC)
SBCCI '06 Proceedings of the 19th annual symposium on Integrated circuits and systems design
Design and verification of high-speed VLSI physical design
Journal of Computer Science and Technology
Proceedings of the 2006 international symposium on Low power electronics and design
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Proceedings of the 39th Annual IEEE/ACM International Symposium on Microarchitecture
Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design
A novel dimensionally-decomposed router for on-chip communication in 3D architectures
Proceedings of the 34th annual international symposium on Computer architecture
Placement of 3D ICs with thermal and interlayer via considerations
Proceedings of the 44th annual Design Automation Conference
Temperature-aware processor frequency assignment for MPSoCs using convex optimization
CODES+ISSS '07 Proceedings of the 5th IEEE/ACM international conference on Hardware/software codesign and system synthesis
Three-dimensional multiprocessor system-on-chip thermal optimization
CODES+ISSS '07 Proceedings of the 5th IEEE/ACM international conference on Hardware/software codesign and system synthesis
Placement of defect-tolerant digital microfluidic biochips using the T-tree formulation
ACM Journal on Emerging Technologies in Computing Systems (JETC)
Thermal-aware Steiner routing for 3D stacked ICs
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
LP based white space redistribution for thermal via planning and performance optimization in 3D ICs
Proceedings of the 2008 Asia and South Pacific Design Automation Conference
MIRA: A Multi-layered On-Chip Interconnect Router Architecture
ISCA '08 Proceedings of the 35th Annual International Symposium on Computer Architecture
Temperature control of high-performance multi-core platforms using convex optimization
Proceedings of the conference on Design, automation and test in Europe
Multidisciplinary heat generating logic block placement optimization using genetic algorithm
Microelectronics Journal
Automated module assignment in stacked-Vdd designs for high-efficiency power delivery
ACM Journal on Emerging Technologies in Computing Systems (JETC)
Three-dimensional Integrated Circuit Design
Three-dimensional Integrated Circuit Design
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IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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Integration, the VLSI Journal
A control theory approach for thermal balancing of MPSoC
Proceedings of the 2009 Asia and South Pacific Design Automation Conference
Congestion-aware power grid optimization for 3D circuits using MIM and CMOS decoupling capacitors
Proceedings of the 2009 Asia and South Pacific Design Automation Conference
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Proceedings of the 2009 Asia and South Pacific Design Automation Conference
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Proceedings of the 2009 Asia and South Pacific Design Automation Conference
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Proceedings of the 2009 Asia and South Pacific Design Automation Conference
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ACM Transactions on Design Automation of Electronic Systems (TODAES)
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IEEE Transactions on Circuits and Systems Part I: Regular Papers
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IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
An analytical placer for mixed-size 3D placement
Proceedings of the 19th international symposium on Physical design
Thermal-aware floorplanning exploration for 3D multi-core architectures
Proceedings of the 20th symposium on Great lakes symposium on VLSI
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Proceedings of the 20th symposium on Great lakes symposium on VLSI
The impact of liquid cooling on 3D multi-core processors
ICCD'09 Proceedings of the 2009 IEEE international conference on Computer design
Integration, the VLSI Journal
TABS: temperature-aware layout-driven behavioral synthesis
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Full-chip thermal analysis for the early design stage via generalized integral transforms
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A high sensitivity and process tolerant digital thermal sensing scheme for 3-D Ics
Proceedings of the 21st edition of the great lakes symposium on Great lakes symposium on VLSI
Thermal via allocation for 3-D ICs considering temporally and spatially variant thermal power
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
TSV-aware analytical placement for 3D IC designs
Proceedings of the 48th Design Automation Conference
Thermal-aware cell and through-silicon-via co-placement for 3D ICs
Proceedings of the 48th Design Automation Conference
Through-silicon-via management during 3D physical design: when to add and how many?
Proceedings of the International Conference on Computer-Aided Design
Three-dimensional Integrated Circuits: Design, EDA, and Architecture
Foundations and Trends in Electronic Design Automation
Recent thermal management techniques for microprocessors
ACM Computing Surveys (CSUR)
Exploiting die-to-die thermal coupling in 3D IC placement
Proceedings of the 49th Annual Design Automation Conference
Spatial and temporal thermal characterization of stacked multicore architectures
ACM Journal on Emerging Technologies in Computing Systems (JETC)
Developing a power-efficient and low-cost 3D NoC using smart GALS-based vertical channels
Journal of Computer and System Sciences
Crosstalk avoidance codes for 3D VLSI
Proceedings of the Conference on Design, Automation and Test in Europe
A network-flow based algorithm for power density mitigation at post-placement stage
Proceedings of the Conference on Design, Automation and Test in Europe
TSV redundancy: architecture and design issues in 3-D IC
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Design space exploration of thermal-aware many-core systems
Journal of Systems Architecture: the EUROMICRO Journal
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As the technology node progresses, thermal problems arebecoming more prominent especially in the developingtechnology of three-dimensional (3D) integrated circuits. Thethermal placement method presented in this paper uses an iterativeforce-directed approach in which thermal forces direct cells awayfrom areas of high temperature. Finite element analysis (FEA) isused to calculate temperatures efficiently during each iteration.Benchmark circuits produce thermal placements with both lowertemperatures and thermal gradients while wirelength is minimally affected.