An efficient implementation of a scaling minimum-cost flow algorithm
Journal of Algorithms
Interconnect characteristics of 2.5-D system integration scheme
Proceedings of the 2001 international symposium on Physical design
An algorithm for integrated pin assignment and buffer planning
Proceedings of the 39th annual Design Automation Conference
Efficient Thermal Placement of Standard Cells in 3D ICs using a Force Directed Approach
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
A thermal-driven floorplanning algorithm for 3D ICs
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
Thermal-driven multilevel routing for 3-D ICs
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
Thermal via planning for 3-D ICs
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
High-performance routing at the nanometer scale
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
Simultaneous buffer and interlayer via planning for 3D floorplanning
ISQED '09 Proceedings of the 2009 10th International Symposium on Quality of Electronic Design
Thermal via allocation for 3-D ICs considering temporally and spatially variant thermal power
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Multilayer pin assignment for macro cell circuits
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Min-cost flow-based algorithm for simultaneous pin assignment and routing
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Efficient Thermal via Planning Approach and Its Application in 3-D Floorplanning
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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Signal through-the-silicon via (STS-via) planning plays an important role in multi-layer nets which need vertical interconnection between different device layers. Moreover, STS-via can also dissipate heat, which is a much more serious problem in 3D ICs than in 2D ICs. Since the through-the-silicon via is large and can only be inserted into whitespace of the device layer, planning STS-via for thermal optimization may affect the interconnection wire length. Therefore, in order to make STS-via planning more flexible, we integrated STS-via with pin assignment. In this paper, we use min-cost maximum flow algorithm for STS-via planning and pin assignment simultaneously. Experimental results show that our approach can reduce both temperature and wire length effectively with short runtime.