Simultaneous buffer and interlayer via planning for 3D floorplanning

Authors:
Xu He;Sheqin Dong;Yuchun Ma;Xianlong Hong
Affiliations:
Tsinghua National Laboratory for Information Science&Technology, Tsinghua University, Beijing, China, 100084;Tsinghua National Laboratory for Information Science&Technology, Tsinghua University, Beijing, China, 100084;Tsinghua National Laboratory for Information Science&Technology, Tsinghua University, Beijing, China, 100084;Tsinghua National Laboratory for Information Science&Technology, Tsinghua University, Beijing, China, 100084
Venue:
ISQED '09 Proceedings of the 2009 10th International Symposium on Quality of Electronic Design
Year:
2009

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Abstract

As technology advances, the interconnect delay among modules plays dominant role in chip performance. Buffer insertion, as a traditional approach to reduce wire delay in 2D ICs, is still necessary in 3D ICs to further optimize interconnects. Since those cross multi-layer nets in 3D ICs need to go through vertical interlayer via, the traditional buffer planning turns into simultaneous buffer and interlayer via planning in 3D ICs. In this paper, we give an efficient buffer and interlayer via planning algorithm with linear complexity, which make sure buffer and interlayer via are inserted as successfully as possible. Experimental results show that 3D ICs can significantly improve the interconnect delay.