Network flows: theory, algorithms, and applications
Network flows: theory, algorithms, and applications
An efficient implementation of a scaling minimum-cost flow algorithm
Journal of Algorithms
A new approach to the pin assignment problem
DAC '88 Proceedings of the 25th ACM/IEEE Design Automation Conference
Interconnect characteristics of 2.5-D system integration scheme
Proceedings of the 2001 international symposium on Physical design
An algorithm for integrated pin assignment and buffer planning
Proceedings of the 39th annual Design Automation Conference
Temperature-aware routing in 3D ICs
ASP-DAC '06 Proceedings of the 2006 Asia and South Pacific Design Automation Conference
Thermal-driven multilevel routing for 3-D ICs
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
Thermal via planning for 3-D ICs
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
Simultaneous buffer and interlayer via planning for 3D floorplanning
ISQED '09 Proceedings of the 2009 10th International Symposium on Quality of Electronic Design
Multilayer pin assignment for macro cell circuits
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Min-cost flow-based algorithm for simultaneous pin assignment and routing
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Efficient Thermal via Planning Approach and Its Application in 3-D Floorplanning
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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As technology advances, 3D ICs is introduced for alleviating the interconnect problem coming with shrinking feature size and increasing integration density. In 3D ICs, one of the key challenges is the vertical interlayer via used for different device layers connection. In this paper, we use min-cost maximum flow algorithm for integrated interlayer via planning and pin assignment for all two-pin nets from one source block to all the other blocks, which make sure interlayer via is inserted as successfully as possible with the shortest wire length. By iteratively using this algorithm with other auxiliary methods on each block, we can deal with the problem for all nets among blocks in 3D ICs. Experimental results show its efficiency and effectiveness. To our knowledge, this is the first algorithm of interlayer via planning with pin assignment for 3D ICs.