Optimized pin assignment for lower routing congestion after floorplanning phase
SLIP '02 Proceedings of the 2002 international workshop on System-level interconnect prediction
An algorithm for simultaneous pin assignment and routing
Proceedings of the 2001 IEEE/ACM international conference on Computer-aided design
Integrated interlayer via planning and pin assignment for 3D ICs
Proceedings of the 11th international workshop on System level interconnect prediction
Pin assignment using stochastic local search constraint programming
CP'09 Proceedings of the 15th international conference on Principles and practice of constraint programming
Integration, the VLSI Journal
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We present a multilayer pin (crossing point) assignment algorithm for macro cell circuits. The pin-assignment algorithm takes advantage of a multilayer chip-level global router that we recently developed. Previously reported methods also sought to combine global routing and pin assignment, but their models forced them to use inferior global routing methods. No previous pin-assignment program can handle multilayer layout in which multiple crossing points should be assigned to cell boundaries to fully minimize total routing length and area. In fact, we will show that multiple crossing-point layouts had 27% less total wire length and 9% less area, on average, than single-pin-assignment solutions