Optimized pin assignment for lower routing congestion after floorplanning phase

Authors:
Tianpei Zhang;Sachin S. Sapatnekar
Affiliations:
University of Minnesota, Minneapolis, MN;University of Minnesota, Minneapolis, MN
Venue:
SLIP '02 Proceedings of the 2002 international workshop on System-level interconnect prediction
Year:
2002

Citing 7
Cited 0

Introduction to algorithms

Introduction to algorithms
A new approach to the pin assignment problem

DAC '88 Proceedings of the 25th ACM/IEEE Design Automation Conference
Integrated floorplanning and interconnect planning

ICCAD '99 Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design
Congestion estimation during top-down placement

Proceedings of the 2001 international symposium on Physical design
Floorplan Evaluation with Timing-Driven Global Wireplanning, Pin Assignment and Buffer/Wire Sizing

ASP-DAC '02 Proceedings of the 2002 Asia and South Pacific Design Automation Conference
Pin assignment with global routing for VLSI building block layout

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Multilayer pin assignment for macro cell circuits

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Quantified Score

Hi-index	0.00

Visualization

Abstract

A technique for the early estimation of congestion after the floorplanning phase is proposed in this paper, based on which an optimized pin assignment algorithm is implemented, aiming at reducing the routing congestion. Experiments show that the optimized pin locations will effectively reduce the total routing congestion violations, and the algorithm complexity is reasonable for application to benchmark circuits.