Randomized rounding: a technique for provably good algorithms and algorithmic proofs
Combinatorica - Theory of Computing
A global router using an efficient approximate multicommodity multiterminal flow algorithm
DAC '91 Proceedings of the 28th ACM/IEEE Design Automation Conference
The network inhibition problem
STOC '93 Proceedings of the twenty-fifth annual ACM symposium on Theory of computing
Performance optimization of VLSI interconnect layout
Integration, the VLSI Journal
Planning buffer locations by network flows
ISPD '00 Proceedings of the 2000 international symposium on Physical design
Buffer block planning for interconnect-driven floorplanning
ICCAD '99 Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design
ICCAD '99 Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design
Approximating Fractional Multicommodity Flow Independent of the Number of Commodities
SIAM Journal on Discrete Mathematics
Provably good global buffering by multi-terminal multicommodity flow approximation
Proceedings of the 2001 Asia and South Pacific Design Automation Conference
A practical methodology for early buffer and wire resource allocation
Proceedings of the 38th annual Design Automation Conference
Provably good global buffering using an available buffer block plan
Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
Faster and Simpler Algorithms for Multicommodity Flow and other Fractional Packing Problems.
FOCS '98 Proceedings of the 39th Annual Symposium on Foundations of Computer Science
A global router with a theoretical bound on the optimal solution
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Global routing by new approximation algorithms for multicommodity flow
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Optimized pin assignment for lower routing congestion after floorplanning phase
SLIP '02 Proceedings of the 2002 international workshop on System-level interconnect prediction
Research directions for coevolution of rules and routers
Proceedings of the 2003 international symposium on Physical design
Post-Layout Gate Sizing for Interconnect Delay and Crosstalk Noise Optimization
ISQED '06 Proceedings of the 7th International Symposium on Quality Electronic Design
IEEE Transactions on Computers
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We describe a new algorithm for floorplan evaluation using timing-driven buffered routing according to a prescribed buffer site map. Specifically, we describe a provably good multi-commodity flow based algorithm that finds a global routing minimizing routing area (wirelength and number of buffers) subject to given constraints on buffer/wire congestion and sink delays. This permits detailed floorplan evaluation, i.e., computing the tradeoff curve between routing area and wire/buffer congestion under any combination of delay and capacity constraints.Our algorithm (1) enforces maximum source/buffer wireloads; (2) enforces wire and buffer congestion constraints by taking into account routing channel capacities and buffer site locations; (3) enforces individual sink delay constraints; (4) performs buffer/wire sizing and layer assignment; and (5) integrates pin assignment with virtually no increase in runtime. Preliminary experiments show that near-optimal results are obtained with a practical runtime.