A global router based on a multicommodity flow model
Integration, the VLSI Journal
Randomized rounding: a technique for provably good algorithms and algorithmic proofs
Combinatorica - Theory of Computing
A global router using an efficient approximate multicommodity multiterminal flow algorithm
DAC '91 Proceedings of the 28th ACM/IEEE Design Automation Conference
Network flows: theory, algorithms, and applications
Network flows: theory, algorithms, and applications
An efficient timing-driven global routing algorithm
DAC '93 Proceedings of the 30th international Design Automation Conference
Computational geometry in C
Optimal wire sizing and buffer insertion for low power and a generalized delay model
ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
Randomized approximation algorithms in combinatorial optimization
Approximation algorithms for NP-hard problems
Buffered Steiner tree construction with wire sizing for interconnect layout optimization
Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design
Performance optimization of VLSI interconnect layout
Integration, the VLSI Journal
Delay bounded buffered tree construction for timing driven floorplanning
ICCAD '97 Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design
Proceedings of the sixth annual ACM-SIAM symposium on Discrete algorithms
Planning buffer locations by network flows
ISPD '00 Proceedings of the 2000 international symposium on Physical design
On switch factor based analysis of coupled RC interconnects
Proceedings of the 37th Annual Design Automation Conference
GTX: the MARCO GSRC technology extrapolation system
Proceedings of the 37th Annual Design Automation Conference
Buffer block planning for interconnect-driven floorplanning
ICCAD '99 Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design
Interconnect tuning strategies for high-performance ICs
Proceedings of the conference on Design, automation and test in Europe
Faster and Simpler Algorithms for Multicommodity Flow and other Fractional Packing Problems.
FOCS '98 Proceedings of the 39th Annual Symposium on Foundations of Computer Science
Approximating Fractional Multicommodity Flow Independent of the Number of Commodities
FOCS '99 Proceedings of the 40th Annual Symposium on Foundations of Computer Science
Provably good global buffering by multi-terminal multicommodity flow approximation
Proceedings of the 2001 Asia and South Pacific Design Automation Conference
A practical methodology for early buffer and wire resource allocation
Proceedings of the 38th annual Design Automation Conference
Routability driven floorplanner with buffer block planning
Proceedings of the 2002 international symposium on Physical design
FAR: fixed-points addition & relaxation based placement
Proceedings of the 2002 international symposium on Physical design
Buffer block planning for interconnect planning and prediction
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - System Level Design
An algorithm for integrated pin assignment and buffer planning
Proceedings of the 39th annual Design Automation Conference
Research directions for coevolution of rules and routers
Proceedings of the 2003 international symposium on Physical design
Practical Approximation Algorithms for Separable Packing Linear Programs
WADS '01 Proceedings of the 7th International Workshop on Algorithms and Data Structures
Floorplan Evaluation with Timing-Driven Global Wireplanning, Pin Assignment and Buffer/Wire Sizing
ASP-DAC '02 Proceedings of the 2002 Asia and South Pacific Design Automation Conference
A buffer planning algorithm with congestion optimization
Proceedings of the 2004 Asia and South Pacific Design Automation Conference
Integrating buffer planning with floorplanning for simultaneous multi-objective optimization
Proceedings of the 2004 Asia and South Pacific Design Automation Conference
Interconnect Planning with Local Area Constrained Retiming
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
An algorithm for integrated pin assignment and buffer planning
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Fast buffer planning and congestion optimization in interconnect-driven floorplanning
ASP-DAC '03 Proceedings of the 2003 Asia and South Pacific Design Automation Conference
A buffer planning algorithm based on dead space redistribution
ASP-DAC '03 Proceedings of the 2003 Asia and South Pacific Design Automation Conference
Improved timing closure by early buffer planning in floor-placement design flow
Proceedings of the 17th ACM Great Lakes symposium on VLSI
An effective buffer planning algorithm for IP based fixed-outline SOC placement
Proceedings of the 17th ACM Great Lakes symposium on VLSI
Buffering global interconnects in structured ASIC design
Integration, the VLSI Journal
Simultaneous shield and buffer insertion for crosstalk noise reduction in global routing
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Handling routability in floorplan design with twin binary trees
Integration, the VLSI Journal
Buffer planning for IP placement using sliced-LFF
VLSI Design - Special issue on CAD for Gigascale SoC Design and Verification Solutions
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To implement high-performance global interconnect without impacting the performance of existing blocks, the use of buffer blocks is increasingly popular in structured-custom and block-based ASIC/SOC methodologies. Recent works by Cong et al. [6] and Tang and Wong [25] give algorithms to solve the buffer block planning problem. In this paper we address the problem of how to perform buffering of global nets given an existing buffer block plan. Assuming as in [6, 25] that global nets have been already decomposed into two-pin connections, we give a provably good algorithm based on a recent approach of Garg and Könemann [8] and Fleischer [7]. Our method routes connections using available buffer blocks, such that required upper and lower bounds on buffer intervals -- as well as wirelength upper bounds per connection -- are satisfied. Unlike [6, 25], our model allows more than one buffer to be inserted into any given connection. In addition, our algorithm observes buffer parity constraints, i.e., it will choose to use an inverter or a buffer (= co-located pair of inverters) according to source and destination signal parity. The algorithm outperforms previous approaches [6] and has been validated on top-level layouts extracted from a recent high-end microprocessor design.