Efficient implementation of retiming
ICCAD '94 Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design
An improved algorithm for minimum-area retiming
DAC '97 Proceedings of the 34th annual Design Automation Conference
Routability-driven repeater block planning for interconnect-centric floorplanning
ISPD '00 Proceedings of the 2000 international symposium on Physical design
Integration, the VLSI Journal - Special issue on timing closure
Integration of retiming with architectural floorplanning
Integration, the VLSI Journal - Special issue on timing closure
Buffer block planning for interconnect-driven floorplanning
ICCAD '99 Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design
Repeater block planning under simultaneous delay and transition time constraints
Proceedings of the conference on Design, automation and test in Europe
A practical methodology for early buffer and wire resource allocation
Proceedings of the 38th annual Design Automation Conference
Provably good global buffering using an available buffer block plan
Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
Flip-Flop and Repeater Insertion for Early Interconnect Planning
Proceedings of the conference on Design, automation and test in Europe
Improved performance and yield with chip master planning design methodology
Proceedings of the 19th ACM Great Lakes symposium on VLSI
Integration, the VLSI Journal
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We present a framework that considers global routing, repeater insertion, and flip-flop relocation for early inter-connect planning. We formulate the interconnect retiming and flip-flop placement problem as a local area constrained retiming problem and solve it as a series of weighted minimum area retiming problems. Our method for early interconnect planning can reduce and even avoid design iterations between physical planning and high level designs. Experimental results show that our method can reduce the number of area violations by an average of 84% in a single interconnect planning step.