Repeater block planning under simultaneous delay and transition time constraints

Optimal wire sizing and buffer insertion for low power and a generalized delay model

ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design

Performance optimization of VLSI interconnect layout

Integration, the VLSI Journal

Wire segmenting for improved buffer insertion

DAC '97 Proceedings of the 34th annual Design Automation Conference

Buffer insertion for noise and delay optimization

DAC '98 Proceedings of the 35th annual Design Automation Conference

Partitioning by iterative deletion

ISPD '99 Proceedings of the 1999 international symposium on Physical design

Noise-aware repeater insertion and wire-sizing for on-chip interconnect using hierarchical moment-matching

Proceedings of the 36th annual ACM/IEEE Design Automation Conference

Routability-driven repeater block planning for interconnect-centric floorplanning

ISPD '00 Proceedings of the 2000 international symposium on Physical design

Buffer block planning for interconnect-driven floorplanning

ICCAD '99 Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design