Performance optimization of VLSI interconnect layout
Integration, the VLSI Journal
Wire segmenting for improved buffer insertion
DAC '97 Proceedings of the 34th annual Design Automation Conference
A new approach to simultaneous buffer insertion and wire sizing
ICCAD '97 Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design
Delay bounded buffered tree construction for timing driven floorplanning
ICCAD '97 Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design
Closed form solution to simultaneous buffer insertion/sizing and wire sizing
Proceedings of the 1997 international symposium on Physical design
Crosstalk constrained global route embedding
ISPD '99 Proceedings of the 1999 international symposium on Physical design
Buffer insertion with accurate gate and interconnect delay computation
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
High-performance bidirectional repeaters
GLSVLSI '00 Proceedings of the 10th Great Lakes symposium on VLSI
Wiring layer assignments with consistent stage delays
SLIP '00 Proceedings of the 2000 international workshop on System-level interconnect prediction
ICCAD '99 Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design
A graph based algorithm for optimal buffer insertion under accurate delay models
Proceedings of the conference on Design, automation and test in Europe
Repeater block planning under simultaneous delay and transition time constraints
Proceedings of the conference on Design, automation and test in Europe
Delay-optimal wiring plan for the microprocessor of high performance computing machines
ASP-DAC '00 Proceedings of the 2000 Asia and South Pacific Design Automation Conference
Hierarchical model order reduction for signal-integrity interconnect synthesis
GLSVLSI '01 Proceedings of the 11th Great Lakes symposium on VLSI
Improved crosstalk modeling for noise constrained interconnect optimization
Proceedings of the 2001 Asia and South Pacific Design Automation Conference
Modeling and analysis of differential signaling for minimizing inductive cross-talk
Proceedings of the 38th annual Design Automation Conference
Simultaneous driver sizing and buffer insertion using a delay penalty estimation technique
Proceedings of the 2002 international symposium on Physical design
Crosstalk noise optimization by post-layout transistor sizing
Proceedings of the 2002 international symposium on Physical design
Technology-based transformations
Logic Synthesis and Verification
Layout-driven area-constrained timing optimization by net buffering
Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
Formulae and applications of interconnect estimation considering shield insertion and net ordering
Proceedings of the 2001 IEEE/ACM international conference on Computer-aided design
Low-power clock distribution using multiple voltages and reduced swings
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Signal integrity management in an SoC physical design flow
Proceedings of the 2003 international symposium on Physical design
Routing methodology for minimizing 1nterconnect energy dissipation
Proceedings of the 13th ACM Great Lakes symposium on VLSI
Post-route gate sizing for crosstalk noise reduction
Proceedings of the 40th annual Design Automation Conference
Layout-driven Timing Optimization by Generalized De Morgan Transform
ASP-DAC '02 Proceedings of the 2002 Asia and South Pacific Design Automation Conference
ICCD '00 Proceedings of the 2000 IEEE International Conference on Computer Design: VLSI in Computers & Processors
Energy Efficient Signaling in Deep Submicron CMOS Technology
ISQED '01 Proceedings of the 2nd International Symposium on Quality Electronic Design
Driver modeling and alignment for worst-case delay noise
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Reduction of coupling effects by optimizing the 3-D configuration of the routing grid
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special section on low power
Sensitivity guided net weighting for placement driven synthesis
Proceedings of the 2004 international symposium on Physical design
A fast algorithm for identifying good buffer insertion candidate locations
Proceedings of the 2004 international symposium on Physical design
Sensitivity guided net weighting for placement driven synthesis
Proceedings of the 2004 international symposium on Physical design
Complexity analysis and speedup techniques for optimal buffer insertion with minimum cost
Proceedings of the 2004 Asia and South Pacific Design Automation Conference
An O(bn^2) Time Algorithm for Optimal Buffer Insertion with b Buffer Types
Proceedings of the conference on Design, Automation and Test in Europe - Volume 2
Wire Planning with Bounded Over-the-Block Wires
ISQED '05 Proceedings of the 6th International Symposium on Quality of Electronic Design
An efficient surface-based low-power buffer insertion algorithm
Proceedings of the 2005 international symposium on Physical design
Proceedings of the 42nd annual Design Automation Conference
True crosstalk aware incremental placement with noise map
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
An O(mn) time algorithm for optimal buffer insertion of nets with m sinks
ASP-DAC '06 Proceedings of the 2006 Asia and South Pacific Design Automation Conference
Reduction of crosstalk noise by optimizing 3-D configuration of the routing grid
ASP-DAC '03 Proceedings of the 2003 Asia and South Pacific Design Automation Conference
Making fast buffer insertion even faster via approximation techniques
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
A perturbation-aware noise convergence methodology for high frequency microprocessors
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
Reliable crosstalk-driven interconnect optimization
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Fast algorithms for slew constrained minimum cost buffering
Proceedings of the 43rd annual Design Automation Conference
An efficient net ordering algorithm for buffer insertion
Proceedings of the 17th ACM Great Lakes symposium on VLSI
A new twisted differential line structure in global bus design
Proceedings of the 44th annual Design Automation Conference
A practical repeater insertion flow
Proceedings of the 18th ACM Great Lakes symposium on VLSI
Logic gates as repeaters (LGR) for area-efficient timing optimization
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A fully polynomial time approximation scheme for timing driven minimum cost buffer insertion
Proceedings of the 46th Annual Design Automation Conference
Shedding physical synthesis area bloat
VLSI Design - Special issue on CAD for Gigascale SoC Design and Verification Solutions
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Buffer insertion has successfully been applied to reduce delay in global interconnect paths; however, existing techniques only optimize delay and timing slack. With the increasing ratio of coupling to total capacitance and the use of aggressive dynamic logic circuit families, noise is becoming a major design bottleneck. We present comprehensive buffer insertion techniques for noise and delay optimization. Our experiments on a microprocessor design show that our approach fixes all noise violations that were identified by a detailed, simulation-based noise analysis tool. Further, we show that the performance penalty induced by optimizing both delay and noise as opposed to only delay is 2%.