Introduction to algorithms
Optimal wire sizing and buffer insertion for low power and a generalized delay model
ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
Wire segmenting for improved buffer insertion
DAC '97 Proceedings of the 34th annual Design Automation Conference
Interconnect design for deep submicron ICs
ICCAD '97 Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design
Buffer insertion for noise and delay optimization
DAC '98 Proceedings of the 35th annual Design Automation Conference
An O(nlogn) time algorithm for optimal buffer insertion
Proceedings of the 40th annual Design Automation Conference
Proceedings of the 42nd annual Design Automation Conference
Buffer insertion in large circuits with constructive solution search techniques
Proceedings of the 43rd annual Design Automation Conference
Repeater scaling and its impact on CAD
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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There are efficient algorithms for net-based buffer insertion but they lead to sub-optimal path delays or unnecessarily large number of buffers due to their lack of global view. This can increase power consumption as well as die area. The ordering of nets for buffer insertion has a crucial impact on the quality of buffering in terms of path delay and the number of used buffers. A good net ordering can extend the local view of any net-based buffer insertion algorithm.In this paper, an efficient O(nlogn) algorithm for net ordering is presented. The net ordering problem is mapped to traditional knapsack problem to obtain an efficient ordering. Experimental results show that our algorithm can meet timing constraints with an 18.8% reduction in the number of buffers on average.