Wire segmenting for improved buffer insertion
DAC '97 Proceedings of the 34th annual Design Automation Conference
Interleaving buffer insertion and transistor sizing into a single optimization
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Meeting delay constraints in DSM by minimal repeater insertion
DATE '00 Proceedings of the conference on Design, automation and test in Europe
An Efficient Buffer Insertion Algorithm for Large Networks Based on Lagrangian Relaxation
ICCD '99 Proceedings of the 1999 IEEE International Conference on Computer Design
Complexity analysis and speedup techniques for optimal buffer insertion with minimum cost
Proceedings of the 2004 Asia and South Pacific Design Automation Conference
Proceedings of the 42nd annual Design Automation Conference
Efficient algorithms for buffer insertion in general circuits based on network flow
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Repeater scaling and its impact on CAD
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
An efficient net ordering algorithm for buffer insertion
Proceedings of the 17th ACM Great Lakes symposium on VLSI
Fast min-cost buffer insertion under process variations
Proceedings of the 44th annual Design Automation Conference
A practical repeater insertion flow
Proceedings of the 18th ACM Great Lakes symposium on VLSI
Circuit-wise buffer insertion and gate sizing algorithm with scalability
Proceedings of the 45th annual Design Automation Conference
ECO timing optimization using spare cells and technology remapping
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Proceedings of the 49th Annual Design Automation Conference
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Most existing buffer insertion algorithms, such as van Ginneken's algorithm, consider only individual nets. As a result, these algorithms tend to over buffer when applied to combinational circuits, since it is difficult to decide how many buffers to insert in each net. Recently, Sze, et al. [1] proposed a path-based algorithm for buffer insertion in combinational circuits. However their algorithm is inefficient for large circuits when there are many critical paths.In this paper, we present a new buffer insertion algorithm for combinational circuits such that the timing requirements are met and the buffer cost is minimized. Our algorithm iteratively inserts buffers in the circuit to improve the circuit delay. The core of this algorithm is simple but effective technique that guides the search for a good buffering solution. Experimental results on ISCAS85 circuits show that our new algorithm on average uses 36% less buffers and runs 3 times faster than Sze's algorithm.