Efficient algorithms for buffer insertion in general circuits based on network flow
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
Buffer insertion in large circuits with constructive solution search techniques
Proceedings of the 43rd annual Design Automation Conference
ECO timing optimization using spare cells
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
Circuit-wise buffer insertion and gate sizing algorithm with scalability
Proceedings of the 45th annual Design Automation Conference
A power-efficient multipin ILP-based routing technique
IEEE Transactions on Circuits and Systems Part I: Regular Papers
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We propose a novel buffer insertion algorithm for handling more general networks, whose underlying topology is a directed acyclic graph rather than just a RC tree. The algorithm finds a global buffering which minimizes buffer area while meeting the timing constraints. We use Lagrangian relaxation to translate the timing constraints to a cost in the objective function, and simplify the resulting objective function using the special structure of the problem we are solving. The core of the algorithm is a local refinement procedure, which iteratively computes the optimal buffering for each edge so as to minimize a weighted area and delay objective. The resulting procedure is fast, and takes full advantage of the slack available on noncritical paths.