Meeting delay constraints in DSM by minimal repeater insertion
DATE '00 Proceedings of the conference on Design, automation and test in Europe
An O(nlogn) time algorithm for optimal buffer insertion
Proceedings of the 40th annual Design Automation Conference
An Efficient Buffer Insertion Algorithm for Large Networks Based on Lagrangian Relaxation
ICCD '99 Proceedings of the 1999 IEEE International Conference on Computer Design
Proceedings of the 42nd annual Design Automation Conference
Accurate estimation of global buffer delay within a floorplan
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
An O(mn) time algorithm for optimal buffer insertion of nets with m sinks
ASP-DAC '06 Proceedings of the 2006 Asia and South Pacific Design Automation Conference
Reap what you sow: spare cells for post-silicon metal fix
Proceedings of the 2008 international symposium on Physical design
A metal-only-ECO solver for input-slew and output-loading violations
Proceedings of the 2009 international symposium on Physical design
New spare cell design for IR drop minimization in Engineering Change Order
Proceedings of the 46th Annual Design Automation Conference
Matching-based minimum-cost spare cell selection for design changes
Proceedings of the 46th Annual Design Automation Conference
Spare cells with constant insertion for engineering change
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
A metal-only-ECO solver for input-slew and output-loading violations
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
ECO timing optimization using spare cells and technology remapping
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
X-architecture obstacles-avoiding routing with ECO consideration
ICC'10 Proceedings of the 14th WSEAS international conference on Circuits
ECO-aware obstacle-avoiding routing tree algorithm
WSEAS Transactions on Circuits and Systems
TRECO: dynamic technology remapping for timing engineering change orders
Proceedings of the 2010 Asia and South Pacific Design Automation Conference
Reconfigurable ECO cells for timing closure and IR drop minimization
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
INTEGRA: fast multi-bit flip-flop clustering for clock power saving based on interval graphs
Proceedings of the 2011 international symposium on Physical design
Simultaneous functional and timing ECO
Proceedings of the 48th Design Automation Conference
Timing ECO optimization via Bézier curve smoothing and fixability identification
Proceedings of the International Conference on Computer-Aided Design
ECO cost measurement and incremental gate sizing for late process changes
ACM Transactions on Design Automation of Electronic Systems (TODAES) - Special section on adaptive power management for energy and temperature-aware computing systems
PushPull: short path padding for timing error resilient circuits
Proceedings of the 2013 ACM international symposium on International symposium on physical design
Intuitive ECO synthesis for high performance circuits
Proceedings of the Conference on Design, Automation and Test in Europe
Clock tree resynthesis for multi-corner multi-mode timing closure
Proceedings of the 2014 on International symposium on physical design
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We introduce in this paper a new problem of ECO timing optimization using spare-cell rewiring and present the first work for this problem. Spare-cell rewiring is a popular technique for incremental timing optimization and/or functional change after the placement stage. The spare-cell rewiring problem is very challenging because of its dynamic wiring cost nature for selecting a spare cell, while the existing related problems consider only static wiring cost. For the addressed problem, we present a framework of buffer insertion and gate sizing to handle it. In this framework, we present a dynamic programming algorithm considering the dynamic cost, called dynamic cost programming (DCP), for the ECO timing optimization with spare cells. Without loss of solution optimality, we further present an effective pruning method by selecting spare cells only inside an essential bounding polygon to reduce the solution space. The whole framework is integrated into a commercial design flow. Experimental results based on five industry benchmarks show that our method is very effective and efficient in fixing the timing violations of ECO paths.