ICCAD '94 Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design
BooleDozer: logic synthesis for ASICs
IBM Journal of Research and Development
Error correction based on verification techniques
DAC '96 Proceedings of the 33rd annual Design Automation Conference
ISPD '00 Proceedings of the 2000 international symposium on Physical design
Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
Incremental Synthesis for Engineering Changes
ICCD '91 Proceedings of the 1991 IEEE International Conference on Computer Design on VLSI in Computer & Processors
Design diagnosis using Boolean satisfiability
Proceedings of the 2004 Asia and South Pacific Design Automation Conference
Diffusion-based placement migration
Proceedings of the 42nd annual Design Automation Conference
Dynamic transition relation simplification for bounded property checking
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
The nuts and bolts of physical synthesis
Proceedings of the 2007 international workshop on System level interconnect prediction
Fixing Design Errors with Counterexamples and Resynthesis
ASP-DAC '07 Proceedings of the 2007 Asia and South Pacific Design Automation Conference
Scalable exploration of functional dependency by interpolation and incremental SAT solving
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
ECO timing optimization using spare cells
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
Improved Design Debugging Using Maximum Satisfiability
FMCAD '07 Proceedings of the Formal Methods in Computer Aided Design
Towards automated ECOs in FPGAs
Proceedings of the ACM/SIGDA international symposium on Field programmable gate arrays
DeltaSyn: an efficient logic difference optimizer for ECO synthesis
Proceedings of the 2009 International Conference on Computer-Aided Design
History-based VLSI legalization using network flow
Proceedings of the 47th Design Automation Conference
TRECO: dynamic technology remapping for timing engineering change orders
Proceedings of the 2010 Asia and South Pacific Design Automation Conference
Interpolation-based incremental ECO synthesis for multi-error logic rectification
Proceedings of the 48th Design Automation Conference
A robust functional ECO engine by SAT proof minimization and interpolation techniques
Proceedings of the International Conference on Computer-Aided Design
Logic synthesis for engineering change
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
AutoFix: a hybrid tool for automatic logic rectification
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
An Efficient Tile-Based ECO Router Using Routing Graph Reduction and Enhanced Global Routing Flow
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
ECO-System: Embracing the Change in Placement
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Hi-index | 0.00 |
In the IC industry, chip design cycles are becoming more compressed, while designs themselves are growing in complexity. These trends necessitate efficient methods to handle late-stage engineering change orders (ECOs) to the functional specification, often in response to errors discovered after much of the implementation is finished. Past ECO synthesis algorithms have typically treated ECOs as functional errors and applied error diagnosis techniques to solve them. However, error diagnosis methods are primarily geared towards finding a single change, and moreover, tend to be computationally complex. In this paper, we propose a unique methodology that can systematically incorporate human intuition into the ECO process. Our methodology involves finding a set of directly substitutable points known as functional correspondences between the original implementation and the new specification by using name-preserving synthesis and user hints, to diminish the size of the ECO problem. On average, our approach can reduce the size of logic changes by 94% from those reported in current literature. We then incorporate our logic ECO changes into an incremental physical synthesis flow to demonstrate its usability in an industrial setting. Our ECO synthesis methodology is evaluated on high-performance industrial designs. Results indicate that post-ECO worst negative slack (WNS) improved 14% and total negative slack (TNS) improved 46% over pre-ECO.