Proceedings of the 42nd annual Design Automation Conference
The impact of the nanoscale on computing systems
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
The nuts and bolts of physical synthesis
Proceedings of the 2007 international workshop on System level interconnect prediction
The coming of age of physical synthesis
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
Timing optimization by restructuring long combinatorial paths
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
RUMBLE: an incremental, timing-driven, physical-synthesis optimization algorithm
Proceedings of the 2008 international symposium on Physical design
Path smoothing via discrete optimization
Proceedings of the 45th annual Design Automation Conference
Blue Gene/L compute chip: synthesis, timing, and physical design
IBM Journal of Research and Development
DeltaSyn: an efficient logic difference optimizer for ECO synthesis
Proceedings of the 2009 International Conference on Computer-Aided Design
Logical and physical restructuring of fan-in trees
Proceedings of the 19th international symposium on Physical design
ITOP: integrating timing optimization within placement
Proceedings of the 19th international symposium on Physical design
Shedding physical synthesis area bloat
VLSI Design - Special issue on CAD for Gigascale SoC Design and Verification Solutions
Design methodology for the IBM POWER7 microprocessor
IBM Journal of Research and Development
SPIRE: a retiming-based physical-synthesis transformation system
Proceedings of the International Conference on Computer-Aided Design
WRIP: logic restructuring techniques for wirelength-driven incremental placement
Proceedings of the great lakes symposium on VLSI
Progress and challenges in VLSI placement research
Proceedings of the International Conference on Computer-Aided Design
Intuitive ECO synthesis for high performance circuits
Proceedings of the Conference on Design, Automation and Test in Europe
CATALYST: planning layer directives for effective design closure
Proceedings of the Conference on Design, Automation and Test in Europe
Depth controlled symmetric function fanin tree restructure
Proceedings of the International Conference on Computer-Aided Design
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With larger chip images and increasingly aggressive technologies, key design processes must interoperate. PDS, a physical-synthesis system, accomplishes technology closure through interacting processes of logic optimization, placement, timing, clock insertion, and routing, all using a common infrastructure with robust variable-accuracy analysis abstractions.